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Kyushu Institute of Technology, Iizuka, Japan
Kyushu Institute of Technology, Iizuka, Japan
Ehime University, Matsuyama, Japan
Kyushu Institute of Technology, Iizuka, Japan
Kyushu Institute of Technology, Iizuka, Japan
抄録
Multi-cycle test with partial observation for scan-based logic BIST is known as one of effective methods to improve fault coverage without increase of test time. In the method, the selection of flip-flops for partial observation is critical to achieve high fault coverage with small area overhead. This paper proposes a selection method under the limitation to a number of flip-flops. The method consists of structural analysis of CUT and logic simulation of test vectors, therefore, it provides an easy implementation and a good scalability. Experimental results on benchmark circuits show that the method obtains higher fault coverage with less area overhead than the original method. Also the relation between the number of selected flip-flops and fault coverage is investigated.
内容記述
27th IEEE ASIAN TEST SYMPOSIUM (ATS'18), 15-18 October 2018, Hefei, China
雑誌名
2018 IEEE 27th Asian Test Symposium (ATS)
発行年
2018-12-10
出版者
IEEE
ISSN
2377-5386
1081-7735
ISBN
978-1-5386-9466-4
978-1-5386-9467-1
DOI
info:doi/10.1109/ATS.2018.00017
権利
Copyright (c) 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST
ATS.2018.00017.pdf
(432.33KB)
