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Si (100)-GaN/Si (111) low temperature wafer bonding process for 3D power supply on chip
http://hdl.handle.net/10228/00007670
http://hdl.handle.net/10228/000076703e96750d-75f9-4bd2-80e0-2573eba51644
名前 / ファイル | ライセンス | アクション |
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nperc145.pdf (987.4 kB)
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Item type | 学術雑誌論文 = Journal Article(1) | |||||||||||
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公開日 | 2020-03-26 | |||||||||||
資源タイプ | ||||||||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||||
資源タイプ | journal article | |||||||||||
タイトル | ||||||||||||
タイトル | Si (100)-GaN/Si (111) low temperature wafer bonding process for 3D power supply on chip | |||||||||||
言語 | ||||||||||||
言語 | eng | |||||||||||
著者 |
Ishito, Ryuki
× Ishito, Ryuki× Ono, Kota× 松本, 聡
WEKO
27142
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抄録 | ||||||||||||
内容記述タイプ | Abstract | |||||||||||
内容記述 | In this paper, we describe the wafer bonding technology Si (100) substrate and GaN/Si (111) substrate using surface activated bonding at room temperature and the removal technique for Si (111) substrate underneath the GaN and buffer layers for 3D power-supply on chip. | |||||||||||
備考 | ||||||||||||
内容記述タイプ | Other | |||||||||||
内容記述 | 9th IEEE CPMT Symposium Japan (ICSJ2019), 18-20 November, 2019, Kyoto University, Kyoto, Japan | |||||||||||
書誌情報 |
2019 IEEE CPMT Symposium Japan (ICSJ) 発行日 2020-02-17 |
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出版社 | ||||||||||||
出版者 | IEEE | |||||||||||
DOI | ||||||||||||
関連タイプ | isVersionOf | |||||||||||
識別子タイプ | DOI | |||||||||||
関連識別子 | https://doi.org/10.1109/ICSJ47124.2019.8998700 | |||||||||||
日本十進分類法 | ||||||||||||
主題Scheme | NDC | |||||||||||
主題 | 549 | |||||||||||
ISSN | ||||||||||||
収録物識別子タイプ | ISSN | |||||||||||
収録物識別子 | 2475-8418 | |||||||||||
ISSN | ||||||||||||
収録物識別子タイプ | ISSN | |||||||||||
収録物識別子 | 2373-5449 | |||||||||||
著作権関連情報 | ||||||||||||
権利情報 | Copyright (c) 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Power-SoC | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | 3D IC | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Wafer bonding technology | |||||||||||
出版タイプ | ||||||||||||
出版タイプ | AM | |||||||||||
出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||||||||
査読の有無 | ||||||||||||
値 | yes | |||||||||||
連携ID | ||||||||||||
8172 | ||||||||||||
資料タイプ | ||||||||||||
内容記述タイプ | Other | |||||||||||
内容記述 | Journal Article | |||||||||||
著者所属 | ||||||||||||
Kyushu Institute Technology | ||||||||||||
著者所属 | ||||||||||||
Kyushu Institute Technology | ||||||||||||
著者所属 | ||||||||||||
Kyushu Institute Technology |