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A universal test structure for the direct measurement of the design margin of even-stage ring oscillators with CMOS latch
http://hdl.handle.net/10228/00007546
http://hdl.handle.net/10228/0000754640d03486-3763-477a-9975-72240d1a7a6b
名前 / ファイル | ライセンス | アクション |
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10229125.pdf (598.2 kB)
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Item type | 会議発表論文 = Conference Paper(1) | |||||||||||
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公開日 | 2020-01-21 | |||||||||||
資源タイプ | ||||||||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||||||||
資源タイプ | conference paper | |||||||||||
タイトル | ||||||||||||
言語 | en | |||||||||||
タイトル | A universal test structure for the direct measurement of the design margin of even-stage ring oscillators with CMOS latch | |||||||||||
その他のタイトル | ||||||||||||
その他のタイトル | A Universal Test Structure for the Direct Measurement of the Design Margin of Even-Stage Ring Oscillators with CMOS Latch | |||||||||||
言語 | en | |||||||||||
言語 | ||||||||||||
言語 | eng | |||||||||||
著者 |
Hirakawa, Yutaka
× Hirakawa, Yutaka× Motomura, Ayami× Ota, Kohei× Mimura, Norihiro× 中村, 和之
WEKO
26231
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抄録 | ||||||||||||
内容記述タイプ | Abstract | |||||||||||
内容記述 | To validate our optimized design theory for Even Stage Ring Oscillators (ESROs), we have developed a Universal ESRO TEG (U-ESRO TEG) constructed with Equivalent Variable-W Transistors (EVWTs) and Initial-voltage Preset-able Inverters (IPIs). The design parameters can be changed with a single circuit, and it is possible to measure the operation margin and oscillation availability of an ESRO. Experimental results confirm the validity of our ESRO design theory. | |||||||||||
言語 | en | |||||||||||
備考 | ||||||||||||
内容記述タイプ | Other | |||||||||||
内容記述 | IEEE International Conference on Microelectronic Test Structures (ICMTS 2012), 19-22 March 2012, San Diego, CA, USA | |||||||||||
書誌情報 |
en : 2012 IEEE International Conference on Microelectronic Test Structures (ICMTS) 発行日 2012-04-26 |
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出版社 | ||||||||||||
出版社 | IEEE | |||||||||||
DOI | ||||||||||||
関連タイプ | isVersionOf | |||||||||||
識別子タイプ | DOI | |||||||||||
関連識別子 | https://doi.org/10.1109/ICMTS.2012.6190605 | |||||||||||
ISBN | ||||||||||||
識別子タイプ | ISBN | |||||||||||
関連識別子 | 978-1-4673-1030-7 | |||||||||||
ISBN | ||||||||||||
識別子タイプ | ISBN | |||||||||||
関連識別子 | 978-1-4673-1027-7 | |||||||||||
ISBN | ||||||||||||
識別子タイプ | ISBN | |||||||||||
関連識別子 | 978-1-4673-1029-1 | |||||||||||
ISSN | ||||||||||||
収録物識別子タイプ | EISSN | |||||||||||
収録物識別子 | 2158-1029 | |||||||||||
ISSN | ||||||||||||
収録物識別子タイプ | PISSN | |||||||||||
収録物識別子 | 1071-9032 | |||||||||||
著作権関連情報 | ||||||||||||
権利情報 | Copyright (c) 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Latches | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Random access memory | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Tin | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Pins | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | CMOS integrated circuits | |||||||||||
キーワード | ||||||||||||
主題Scheme | Other | |||||||||||
主題 | Inverters | |||||||||||
出版タイプ | ||||||||||||
出版タイプ | AM | |||||||||||
出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||||||||
査読の有無 | ||||||||||||
値 | yes | |||||||||||
研究者情報 | ||||||||||||
https://hyokadb02.jimu.kyutech.ac.jp/html/381_ja.html | ||||||||||||
論文ID(連携) | ||||||||||||
10229125 | ||||||||||||
連携ID | ||||||||||||
8055 | ||||||||||||
資料タイプ | ||||||||||||
内容記述タイプ | Other | |||||||||||
内容記述 | Conference Paper |