@article{oai:kyutech.repo.nii.ac.jp:00001628,
 author = {Wen, Xiaoqing and 温, 暁青 and Miyase, Kohei and 宮瀬, 紘平 and Suzuki, Tatsuya and Kajihara, Seiji and 梶原, 誠司 and Wang, Laung-Terng and Saluja, K. Kewal and Kinoshita, Kozo},
 issue = {4},
 journal = {Journal of Electronic Testing},
 month = {Aug},
 note = {At-speed scan testing, based on ATPG and ATE, is indispensable to guarantee timing-related test quality in the DSM era. However, at-speed scan testing may incur yield loss due to excessive IR-drop caused by high test (shift & capture) switching activity. This paper discusses the mechanism of circuit malfunction due to IR-drop, and summarizes general approaches to reducing switching activity, by which highlights the problem of current solutions, i.e. only reducing switching activity for one capture while the widely used at-speed scan testing based on the launch-off-capture scheme uses two captures. This paper then proposes a novel X-filling method, called double-capture (DC) X-filling, for generating test vectors with low and balanced capture switching activity for two captures. Applicable to dynamic & static compaction in any ATPG system, DC X-filling can reduce IR-drop, and thus yield loss, without any circuit/clock modification, timing/circuit overhead, fault coverage loss, and additional design effort.},
 pages = {379--391},
 title = {Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing},
 volume = {24},
 year = {2008},
 yomi = {オン, ギョウセイ and ミヤセ, コウヘイ and カジハラ, セイジ}
}