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  1. 学術雑誌論文
  2. 5 技術(工学)

LUTNet-RC: Look-Up Tables Networks for Reservoir Computing on an FPGA

http://hdl.handle.net/10228/0002000603
http://hdl.handle.net/10228/0002000603
91e38983-a9ce-4b52-9346-f6bc57c75d19
名前 / ファイル ライセンス アクション
10429120.pdf 10429120.pdf (3 MB)
アイテムタイプ 学術雑誌論文 = Journal Article(1)
公開日 2024-05-09
資源タイプ
資源タイプ識別子 http://purl.org/coar/resource_type/c_6501
資源タイプ journal article
タイトル
タイトル LUTNet-RC: Look-Up Tables Networks for Reservoir Computing on an FPGA
言語 en
言語
言語 eng
著者 Yoshioka, Kanta

× Yoshioka, Kanta

en Yoshioka, Kanta

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田中, 悠一朗

× 田中, 悠一朗

WEKO 30537
e-Rad_Researcher 70911288
Scopus著者ID 57197734548
ORCiD 0000-0001-6974-070X
九工大研究者情報 100001426

en Tanaka, Yuichiro

ja 田中, 悠一朗


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田向, 権

× 田向, 権

WEKO 6059
e-Rad_Researcher 90432955
Scopus著者ID 7801453348
ORCiD 0000-0002-3669-1371
九工大研究者情報 100000641

en Tamukoh, Hakaru

ja 田向, 権


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抄録
内容記述タイプ Abstract
内容記述 We propose look-up tables networks-based reservoir computing (LUTNet-RC). This work is the first trial of applying LUTNets to RC. LUTNet-RC consists of a LUT-based reservoir layer and a non-LUT-based output layer. LUTNets have disadvantages such as limited sparse connectivity and weights cannot be changed after implementation. However, when applied to a reservoir layer of RC (LUT-based reservoir layer), these disadvantages are eliminated, because this layer works with sparse connectivity and the weights are fixed, so only the advantage of small circuit resources is obtained. For the LUT-based reservoir layer, we propose and model a multi-bit weight reservoir, modifying the conventional binarized reservoir to improve calculation accuracy. In the case of LUTNets, the proposed multi-bit weight reservoir can be implemented without the increase in utilized circuit resources because LUTNets focus only on the input-output relationship on neurons. Additionally, we propose a speed-up method in the output layer with time division calculation, which compares the current network state with previous states and then calculates only status-changed neurons. As a result, we implement a LUTNet-RC with 1500 reservoir neurons on a field-programmable gate array (KR260) running at 100MHz. The utilized circuit resources are dominated by LUTs, which use approximately 26% of the total amount of LUTs. The LUTNet-RC can infer more than 10 6 data per second. We also verify the LUTNet-RC performance using nonlinear auto-regressive moving average 10 (NARMA10) and the performance is comparable to conventional works. We conclude that the LUTNet-RC is one of the highest-performance RC on an FPGA.
言語 en
備考
内容記述タイプ Other
内容記述 2023 International Conference on Field Programmable Technology (ICFPT), 12-14 December 2023, Yokohama, Japan
言語 en
書誌情報 en : 2023 International Conference on Field Programmable Technology (ICFPT)

p. 170-178, 発行日 2024-02-01
出版社
出版者 IEEE
DOI
関連タイプ isVersionOf
識別子タイプ DOI
関連識別子 https://doi.org/10.1109/ICFPT59805.2023.00024
ISBN
識別子タイプ ISBN
関連識別子 979-8-3503-5912-1
ISBN
識別子タイプ ISBN
関連識別子 979-8-3503-5911-4
ISSN
収録物識別子タイプ PISSN
収録物識別子 2837-0430
ISSN
収録物識別子タイプ EISSN
収録物識別子 2837-0449
著作権関連情報
権利情報 Copyright (c) 2024 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
キーワード
主題Scheme UDC
主題 neural networks
キーワード
主題Scheme Other
主題 reservoir computing
キーワード
主題Scheme Other
主題 field programmable gate array
出版タイプ
出版タイプ AM
出版タイプResource http://purl.org/coar/version/c_ab4af688f83e57aa
査読の有無
値 yes
研究者情報
URL https://hyokadb02.jimu.kyutech.ac.jp/html/100001426_ja.html
論文ID(連携)
値 10429120
連携ID
値 12178
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