IR-Drop-Aware Testing for Mitigating Test-Induced Yield Loss

Shi, Shiling

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テストによる歩留まり低下を軽減するためのIRドロップ考慮型テストに関する研究

https://doi.org/10.18997/0002001051

名前 / ファイル	ライセンス	アクション
jou_k_405.pdf (9 MB)

アイテムタイプ

学位論文 = Thesis or Dissertation(1)

公開日

2024-11-20

資源タイプ

資源タイプ識別子

http://purl.org/coar/resource_type/c_db06

資源タイプ

doctoral thesis

タイトル

IR-Drop-Aware Testing for Mitigating Test-Induced Yield Loss

言語

タイトル

テストによる歩留まり低下を軽減するためのIRドロップ考慮型テストに関する研究

言語

jpn

著者

Shi, Shiling

抄録

内容記述タイプ

Abstract

内容記述

With an ever-increasing demand for high-performance and power-efficient Integrated Circuits (ICs), power consumption has become the most critical constraint in IC design. Power reduction is growing even more complicated as Artificial Intelligence (AI) is increasingly used in IoT and mobile devices. Elaborate power management strategies are developed today to control the power consumption during functional operation. However, power issues are not confined to functional operation only and also manifest during IC testing, threatening the quality and costs of IC testing for low-power circuits. The reason is that test power can be much higher than functional power. Severe IR-drop may occur due to excessive test power, incurring extra gate delay or even erroneously change the logic state of cells. This will cause a good CUT to fail the test, resulting in testrelated yield loss on top of process-related yield loss. This situation is getting even worse as the nominal supply voltage is scaling down further and further in modern technologies.
To improve test quality and reduce test cost, scan design, the most common DFT technique, is well supported by test engineers. In scan design, scan flip-flops replace all flip-flops and are connected to form multiple shift registers (i.e. scan chains) to shift in test vectors and shift out test responses. On the other hand, test vectors are generated during ATPG by targeting as many faults that would result from defects in the manufactured circuit as possible. Due to test time and test cost constraints, all scan chains are usually activated to shifting test vectors. As a result, shift operations cause unusually high Shift Switching Activity (SSA), leading to excessive peak IR-drop in some shift cycles. These excessive peak IRdrop must be reduced as they can cause wrong data to be shifted and circuit to falsely fail the test. This unique challenge posed by power consumption during scan shift introduces a new dimension to both DFT and ATPG.
Clearly, the key component in any IR-drop mitigation methods is IR-drop estimation. However, most of test application time is spent in shift cycles. Every shift cycle must be first simulated to generate necessary SSA data. Applying SSA to IR-drop estimations is still computationally demanding as it implies solving systems of linear equations repeatedly. Past researches often used approximation metrics, such as Flip-Flop Toggle Count (FFTC) and Weighted Switching Activity (WSA), to estimate IR drop or test power. However, the above metrics do not correlate well with IR drop.
One class of existing low shift IR-drop techniques is DFT-based to change the scan chain clocking. The principle of reducing excessive SSA-induced IR-drop is to add additional cycles so that scan chains can not be shifted simultaneously. However, they just enable partial scan chains at each time, leading to a considerable test time penalty. Another one is ATPG-based to assign logic values to the unspecified bits (X-bits) in a test cube so that the resulting fully-specified test vector has low SSA. However, the actual effect of previous X-filling methods is often unclear since they only reduce overall switching activity that is not directly related to the mechanism of test-induced yield loss.
This thesis presents contributions to facilitate IR-drop-aware scan shift to obtain
potential gains in shift safety and reduce test-induced yield-loss:
Contribution-1: A fast dynamic IR-drop simulator with GPU-acceleration, called Cycle-Based IR-Drop Estimation (CIDE), that is a feasible solution to this kind of IR-drop estimation during scan test.
Contribution-2: A novel Scan Shift Schedule that can efficiently reduce shift IR-drop with a low impact on test time by enabling partial scan chains in a targeted manner.
Contribution-3: A novel IR-Drop-Aware X-Filling that can reduce shift IRdrop without incurring impact on fault coverage or test vector count by adjusting X-bits to avoid only high-impact scan-cell transitions.

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備考

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Other

内容記述

九州工業大学博士学位論文学位記番号:情工博甲第405号学位授与年月日:令和6年9月25日

学位授与番号

甲第405号

学位名

博士（情報工学）

学位授与年月日

2024-09-25

学位授与機関

学位授与機関識別子Scheme

kakenhi

学位授与機関識別子

17104

学位授与機関名

九州工業大学

言語

学位授与年度

内容記述タイプ

Other

内容記述

令和6年度

出版タイプ

VoR

出版タイプResource

http://purl.org/coar/version/c_970fb48d4fbd8a85

アクセス権

open access

アクセス権URI

http://purl.org/coar/access_right/c_abf2

ID登録

10.18997/0002001051

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JaLC

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テストによる歩留まり低下を軽減するためのIRドロップ考慮型テストに関する研究

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