| アイテムタイプ |
共通アイテムタイプ(1) |
| 公開日 |
2025-02-05 |
| タイトル |
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|
タイトル |
A Low-Area Overhead and Low-Delay Triple-Node-Upset Self-Recoverable Design Based on Stacked Transistors |
|
言語 |
en |
| 著者 |
Xu, Hui
Li, Jiuqi
Ma, Ruijun
Liang, Huaguo
Liu, Chaoming
Wang, Senling
温, 暁青
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| 著作権関連情報 |
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権利情報 |
Copyright (c) 2024 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. |
| 抄録 |
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内容記述タイプ |
Abstract |
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内容記述 |
With the aggressive scaling in the feature size of transistors, single-event triple-node-upsets (TNUs) induced by charge sharing in CMOS circuits have become a significant reliability problem. In this paper, based on N-type stacked transistors, a TNU self-recovery latch called LORD-TNU is proposed. Utilizing the stacked transistors to reduce the count of sensitive nodes in the latch. In addition, we use three modules to protect each other. In the event of a soft error in one module, the remaining modules can restore the corrupted module. This design not only saves delay overhead but also minimizes area overhead. Simulation results show that compared with the four typical TNU hardened latches, the proposed LORD-TNU latch reduces area overhead by 49.76%, power consumption by 56.07%, delay by 40.17%, and the power-delay-product (PDP) by 72.56% on average, respectively. Moreover, the robustness of our LORD-TNU latch is confirmed by comprehensive PVT (Process, Voltage, Temperature) and Monte Carlo simulations, demonstrating its stability across a range of process corners, supply voltage, and temperature variations. |
|
言語 |
en |
| 書誌情報 |
en : IEEE Transactions on Device and Materials Reliability
巻 24,
号 2,
p. 302-312,
発行日 2024-04-10
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| 出版社 |
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出版者 |
IEEE |
| キーワード |
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主題Scheme |
Other |
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主題 |
Circuit reliability |
| キーワード |
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|
主題Scheme |
Other |
|
主題 |
radiation hardening |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
single event-upset |
| キーワード |
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|
主題Scheme |
Other |
|
主題 |
stacked transistors |
| キーワード |
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|
主題Scheme |
Other |
|
主題 |
triple-node-upset |
| 言語 |
|
|
言語 |
eng |
| 資源タイプ |
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|
資源タイプ識別子 |
http://purl.org/coar/resource_type/c_6501 |
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資源タイプ |
journal article |
| 出版タイプ |
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|
出版タイプ |
AM |
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出版タイプResource |
http://purl.org/coar/version/c_ab4af688f83e57aa |
| DOI |
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|
識別子タイプ |
DOI |
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関連識別子 |
https://doi.org/10.1109/TDMR.2024.3386954 |
| ISSN |
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収録物識別子タイプ |
PISSN |
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収録物識別子 |
1530-4388 |
| ISSN |
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収録物識別子タイプ |
EISSN |
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収録物識別子 |
1558-2574 |
| 研究者情報 |
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URL |
https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html |
| 論文ID（連携） |
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|
値 |
10441918 |
| 連携ID |
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|
値 |
12831 |
10441918.pdf (2.1 MB)
