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A new die-level flexible design-for-test architecture for 3D stacked ICs
http://hdl.handle.net/10228/0002001243
http://hdl.handle.net/10228/000200124363693d36-4801-4cc1-a0f1-cefd5dbf0ce4
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
10441931.pdf (1008 KB)
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| アイテムタイプ | 共通アイテムタイプ(1) | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 公開日 | 2025-02-05 | |||||||||
| タイトル | ||||||||||
| タイトル | A new die-level flexible design-for-test architecture for 3D stacked ICs | |||||||||
| 言語 | en | |||||||||
| その他のタイトル | ||||||||||
| その他のタイトル | An New Design-for-test Architecture of Die-level for 3D Stacked ICs | |||||||||
| 言語 | en | |||||||||
| 著者 |
Zhang, Qingping
× Zhang, Qingping
× Zhan, Wenfa
× 温, 暁青 |
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| 著作権関連情報 | ||||||||||
| 権利情報 | Copyright (c) 2024 Elsevier B.V. All rights reserved. | |||||||||
| 抄録 | ||||||||||
| 内容記述タイプ | Abstract | |||||||||
| 内容記述 | A die-level design-for-test architecture for 3D stacked ICs is proposed. The main component of this architecture is a newly proposed configurable boundary cell, based on which flexible parallel test is achieved. Both of the number of parallel scan chains and their lengths can be configured during test. This test architecture features light-weight, high flexibility in parallel test configuration, modularity, and IEEE P1149.1 compatibility. In this work, both infrastructure and implementation aspects are illustrated. Experimental results demonstrate desired test acceleration. The acceleration ratio approximately reaches its limit, which equals the number of parallel scan chains, when the number of test vectors is over 300. | |||||||||
| 言語 | en | |||||||||
| 書誌情報 |
en : Integration 巻 97, p. 102190, 発行日 2024-04-12 |
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| 出版社 | ||||||||||
| 出版者 | Elsevier | |||||||||
| 言語 | ||||||||||
| 言語 | eng | |||||||||
| 資源タイプ | ||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||
| 資源タイプ | journal article | |||||||||
| 出版タイプ | ||||||||||
| 出版タイプ | AM | |||||||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||||||
| DOI | ||||||||||
| 識別子タイプ | DOI | |||||||||
| 関連識別子 | https://doi.org/10.1016/j.vlsi.2024.102190 | |||||||||
| ISSN | ||||||||||
| 収録物識別子タイプ | PISSN | |||||||||
| 収録物識別子 | 0167-9260 | |||||||||
| ISSN | ||||||||||
| 収録物識別子タイプ | EISSN | |||||||||
| 収録物識別子 | 1872-7522 | |||||||||
| 研究者情報 | ||||||||||
| URL | https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html | |||||||||
| 論文ID（連携） | ||||||||||
| 値 | 10441931 | |||||||||
| 連携ID | ||||||||||
| 値 | 12833 | |||||||||
