| アイテムタイプ |
共通アイテムタイプ(1) |
| 公開日 |
2025-02-05 |
| タイトル |
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|
タイトル |
Efficient design approaches to CMOS full adder circuits |
|
言語 |
en |
| 著者 |
Yan, Aibin
Bao, Han
Jiang, Wangjin
Cui, Jie
Huang, Zhengfeng
温, 暁青
|
| 著作権関連情報 |
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|
権利情報 |
Copyright (c) 2024 Elsevier Ltd. All rights are reserved, including those for text and data mining, AI training, and similar technologies. |
| 抄録 |
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|
内容記述タイプ |
Abstract |
|
内容記述 |
In the field of high-performance chip designs, many applications have the ability to tolerate small errors through the use of approximate full adders. By appropriately reducing the corresponding precision, the performance of hardware implementation can be greatly improved. The adders are commonly applied in digital signal processors (DSP), communication systems, image processing, etc., to quickly complete addition estimation operations. This paper proposes the designs of 8 approximate adders and compares their performance with existing circuit structures. Simulation results demonstrate that the approximate adders proposed in the first group (i.e., LCAFA1∼LCAFA3) achieve an average area reduction of 21.44 % and an average delay reduction of 42.85 %. In the second group, the proposed approximate adders LCAFA4∼LCAFA8 achieve an average power reduction of 28.35 %, an average area reduction of 17.39 %, an average delay reduction of 84.25 %, and an average decrease in the power-area-delay product (PADP) of 68.26 %. |
|
言語 |
en |
| 書誌情報 |
en : Microelectronics Journal
巻 149,
p. 106235,
発行日 2024-05-08
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| 出版社 |
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出版者 |
Elsevier |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
Approximate calculation |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
Approximate full adder |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
Image processing |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
CMOS |
| 言語 |
|
|
言語 |
eng |
| 資源タイプ |
|
|
資源タイプ識別子 |
http://purl.org/coar/resource_type/c_6501 |
|
資源タイプ |
journal article |
| 出版タイプ |
|
|
出版タイプ |
AM |
|
出版タイプResource |
http://purl.org/coar/version/c_ab4af688f83e57aa |
| DOI |
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|
識別子タイプ |
DOI |
|
|
関連識別子 |
https://doi.org/10.1016/j.mejo.2024.106235 |
| ISSN |
|
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収録物識別子タイプ |
PISSN |
|
収録物識別子 |
0959-8324 |
| ISSN |
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収録物識別子タイプ |
EISSN |
|
収録物識別子 |
1879-2391 |
| 研究者情報 |
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|
URL |
https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html |
| 論文ID（連携） |
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|
値 |
10444055 |
| 連携ID |
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|
値 |
12834 |
10444055.pdf (713 KB)
