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  1. 学術雑誌論文
  2. 5 技術(工学)

An Implementation Method Using Cut-Off Bits for Restricted Boltzmann Machines Without Random Number Generators

http://hdl.handle.net/10228/0002001330
http://hdl.handle.net/10228/0002001330
5c6c90fc-d505-4357-a684-5ff5db907a0b
名前 / ファイル ライセンス アクション
10444481.pdf 10444481.pdf (890 KB)
Item type 共通アイテムタイプ(1)
公開日 2025-02-17
タイトル
タイトル An Implementation Method Using Cut-Off Bits for Restricted Boltzmann Machines Without Random Number Generators
言語 en
著者 Hori, Sansei

× Hori, Sansei

en Hori, Sansei
Hori, S.

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田向, 権

× 田向, 権

WEKO 6059
e-Rad_Researcher 90432955
Scopus著者ID 7801453348
ORCiD 0000-0002-3669-1371
九工大研究者情報 100000641

en Tamukoh, Hakaru

ja 田向, 権

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著作権関連情報
権利情報Resource https://creativecommons.org/licenses/by/4.0/
権利情報 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
抄録
内容記述タイプ Abstract
内容記述 This study proposes an implementation method of a hardware-oriented restricted Boltzmann machine (RBM) without random number generators (RNGs) that employ cut-off bits, which are obtained from fixed-point binary arithmetic operations on digital hardware, such as field-programmable gate arrays (FPGAs), instead of random numbers. Most FPGA circuits employ fixed-point binary arithmetic operations to improve hardware resource efficiency. Therefore, the proposed method applies the unique feature of the operation, which is bit width extension and cut-off bits. Stochastic neural networks, including RBMs, employ sampling processes based on a probability distribution associated with the network, and the processes require many random numbers. However, implementing RNGs in hardware is costly because it requires considerable hardware resources. The proposed method can mitigate this requirement. To validate the proposed method, we implement an RBM with the proposed method on the software, emulate fixed-point binary arithmetic operations, and train the RBM using the MNIST and Fashion MNIST datasets. Furthermore, we apply the chi-square goodness-of-fit test to evaluate the uniformity of the cut-off bits. Additionally, we compare hardware resource requirements and power consumption for the proposed method and some major RNGs, a linear feedback shift register (LFSR), and a xorshift. Experimental results showed that it was possible to use the cut-off bits for training the RBM using the datasets and clarified the properties of the cut-off bits using statistical analyses. Moreover, hardware implementation of the proposed method involved the lowest hardware resource requirements and power consumption among the RNGs compared in this study.
言語 en
書誌情報 en : IEEE Access

巻 10, p. 42791-42801, 発行日 2022-04-18
出版社
出版者 IEEE
キーワード
主題Scheme Other
主題 Field-programmable gate arrays
キーワード
主題Scheme Other
主題 neural networks
キーワード
主題Scheme Other
主題 random number generation
キーワード
主題Scheme Other
主題 restricted Boltzmann machines
言語
言語 eng
資源タイプ
資源タイプ識別子 http://purl.org/coar/resource_type/c_6501
資源タイプ journal article
出版タイプ
出版タイプ VoR
出版タイプResource http://purl.org/coar/version/c_970fb48d4fbd8a85
DOI
識別子タイプ DOI
関連識別子 https://doi.org/10.1109/ACCESS.2022.3168026
助成情報
助成機関名 UENO SEIKI Next Generation Frontier Technology Collaboration Laboratory
言語 en
ISSN
収録物識別子タイプ EISSN
収録物識別子 2169-3536
研究者情報
URL https://hyokadb02.jimu.kyutech.ac.jp/html/100000641_ja.html
論文ID(連携)
値 10444481
連携ID
値 12628
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