{"created":"2023-05-15T11:55:24.659113+00:00","id":324,"links":{},"metadata":{"_buckets":{"deposit":"649478f9-3a2a-4f47-b353-deb219196cac"},"_deposit":{"created_by":3,"id":"324","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"324"},"status":"published"},"_oai":{"id":"oai:kyutech.repo.nii.ac.jp:00000324","sets":["8:24"]},"author_link":["1630","1629","1628","1625","1631","1627","1615"],"item_21_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2004","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3-4","bibliographicPageEnd":"179","bibliographicPageStart":"173","bibliographicVolumeNumber":"15","bibliographic_titles":[{"bibliographic_title":"Journal of Intelligent and Fuzzy Systems"}]}]},"item_21_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Hierarchical convolutional neural networks represent a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent vision systems, its VLSI implementation with high performance and low power consumption is required. This paper proposes a VLSI convolutional network architecture using a hybrid approach composed of pulse-width modulation (PWM) and digital circuits. We call this approach merged/mixed analog-digital architecture. The VLSI chip includes PWM neuron circuits, PWM/digital converters, digital adder-subtracters, and digital memory. We have designed and fabricated a VLSI chip by using a 0.35 μm CMOS process. The VLSI chip can perform 6-bit precision convolution calculations for an image of 100 × 100 pixels with a receptive field area of up to 20 × 20 pixels within 5 ms, which means a performance of 2 GOPS. Power consumption of PWM neuron circuits was measured to be 20 mW. We have verified successful operations using a fabricated VLSI chip.","subitem_description_type":"Abstract"}]},"item_21_description_60":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"subitem_description":"Journal Article","subitem_description_type":"Other"}]},"item_21_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"affiliations":[{"affiliationNames":[{"affiliationName":"","lang":"ja"}],"nameIdentifiers":[]}],"familyNames":[{"familyName":"Morie","familyNameLang":"en"},{"familyName":"森江","familyNameLang":"ja"},{"familyName":"モリエ","familyNameLang":"ja-Kana"}],"givenNames":[{"givenName":"Takashi","givenNameLang":"en"},{"givenName":"隆","givenNameLang":"ja"},{"givenName":"タカシ","givenNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"1615","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"20294530","nameIdentifierScheme":"e-Rad","nameIdentifierURI":"https://nrid.nii.ac.jp/ja/nrid/1000020294530"},{"nameIdentifier":"7005143434","nameIdentifierScheme":"Scopus著者ID","nameIdentifierURI":"https://www.scopus.com/authid/detail.uri?authorId=7005143434"},{"nameIdentifier":"339","nameIdentifierScheme":"九工大研究者情報","nameIdentifierURI":"https://hyokadb02.jimu.kyutech.ac.jp/html/339_ja.html"}],"names":[{"name":"Morie, Takashi","nameLang":"en"},{"name":"森江, 隆","nameLang":"ja"},{"name":"モリエ, タカシ","nameLang":"ja-Kana"}]}]},"item_21_publisher_7":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IOS Press"}]},"item_21_relation_14":{"attribute_name":"情報源","attribute_value_mlt":[{"subitem_relation_name":[{"subitem_relation_name_text":"https://www.iospress.nl/journal/journal-of-intelligent-fuzzy-systems/"}],"subitem_relation_type_id":{"subitem_relation_type_id_text":"https://www.iospress.nl/journal/journal-of-intelligent-fuzzy-systems/","subitem_relation_type_select":"URI"}}]},"item_21_rights_13":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"Copyright © IOS Press"}]},"item_21_select_59":{"attribute_name":"査読の有無","attribute_value_mlt":[{"subitem_select_item":"yes"}]},"item_21_source_id_8":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1064-1246","subitem_source_identifier_type":"ISSN"}]},"item_21_text_36":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Life Science and Systems, Engineering, Kyushu Institute of Technology, Kitakyushu, 808-0196, Japan"},{"subitem_text_value":"Graduate School of Life Science and Systems, Engineering, Kyushu Institute of Technology, Kitakyushu, 808-0196, Japan"},{"subitem_text_value":"Canon Research Center, Atsugi, 243-0193, Japan"},{"subitem_text_value":"Graduate School of Advanced Sciences of Matter, Hiroshima University, Higashi-Hiroshima, 739-8526, Japan"},{"subitem_text_value":"Graduate School of Life Science and Systems, Engineering, Kyushu Institute of Technology, Kitakyushu, 808-0196, Japan"},{"subitem_text_value":"Canon Research Center, Atsugi, 243-0193, Japan"},{"subitem_text_value":"Graduate School of Advanced Sciences of Matter, Hiroshima University, Higashi-Hiroshima, 739-8526, Japan"}]},"item_21_version_type_58":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_ab4af688f83e57aa","subitem_version_type":"AM"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Korekado, Keisuke"}],"nameIdentifiers":[{}]},{"creatorAffiliations":[{"affiliationNameIdentifiers":[],"affiliationNames":[{"affiliationName":""}]}],"creatorNames":[{"creatorName":"Morie, Takashi","creatorNameLang":"en"},{"creatorName":"森江, 隆","creatorNameLang":"ja"},{"creatorName":"モリエ, タカシ","creatorNameLang":"ja-Kana"}],"familyNames":[{},{},{}],"givenNames":[{},{},{}],"nameIdentifiers":[{},{},{},{}]},{"creatorNames":[{"creatorName":"Nomura, Osamu"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Ando, Hiroshi"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Nakano, Teppei"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Matsugu, Masakazu"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Iwata, Atsushi"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2007-12-26"}],"displaytype":"detail","filename":"kore04-jif-draft.pdf","filesize":[{"value":"874.8 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"kore04-jif-draft.pdf","url":"https://kyutech.repo.nii.ac.jp/record/324/files/kore04-jif-draft.pdf"},"version_id":"fbc3387b-c1a2-4d29-92ad-841c9b0bead8"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"A VLSI Convolutional Neural Network for Image Recognition Using Merged/Mixed Analog-Digital Architecture","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"A VLSI Convolutional Neural Network for Image Recognition Using Merged/Mixed Analog-Digital Architecture"}]},"item_type_id":"21","owner":"3","path":["24"],"pubdate":{"attribute_name":"公開日","attribute_value":"2007-12-26"},"publish_date":"2007-12-26","publish_status":"0","recid":"324","relation_version_is_last":true,"title":["A VLSI Convolutional Neural Network for Image Recognition Using Merged/Mixed Analog-Digital Architecture"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2023-10-25T10:55:53.074186+00:00"}