{"created":"2023-05-15T11:55:24.700195+00:00","id":325,"links":{},"metadata":{"_buckets":{"deposit":"98864558-6192-45c4-9385-10084a6e7cc7"},"_deposit":{"created_by":3,"id":"325","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"325"},"status":"published"},"_oai":{"id":"oai:kyutech.repo.nii.ac.jp:00000325","sets":["8:24"]},"author_link":["1635","1615","1633","1636"],"item_21_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2000","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"160","bibliographicPageStart":"154","bibliographicVolumeNumber":"11","bibliographic_titles":[{"bibliographic_title":"Nanotechnology"}]}]},"item_21_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"A new single-electron circuit using the unique features of single-electron devices is proposed, based on a basic strategy and circuit architecture for achieving large-scale integration. A unit circuit consisting of a single-electron transistor and a capacitor operates as an exclusive-NOR gate by the Coulomb blockade effect, and its transient behaviour is stochastic due to electron-tunnelling events. Using this unit circuit, a stochastic associative processing circuit is proposed, based on a new information-processing principle where the association probability depends on the similarity between the input and reference data. This circuit can be constructed by using a silicon nanocrystal floating-gate structure in which dots are regularly arranged on a gate electrode of a MOSFET. The simulation results of a simple digit pattern association demonstrate the successful stochastic operation. The background-charge effects on the proposed circuit are analysed and simulated, and it is shown that the circuit is much more robust to such effects than the conventional single-electron logic circuits.","subitem_description_type":"Abstract"}]},"item_21_description_60":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"subitem_description":"Journal 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Takashi","nameLang":"en"},{"name":"森江, 隆","nameLang":"ja"},{"name":"モリエ, タカシ","nameLang":"ja-Kana"}]}]},"item_21_publisher_7":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IOP Publishing"}]},"item_21_relation_12":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"https://doi.org/10.1088/0957-4484/11/3/303","subitem_relation_type_select":"DOI"}}]},"item_21_relation_14":{"attribute_name":"情報源","attribute_value_mlt":[{"subitem_relation_name":[{"subitem_relation_name_text":"http://www.iop.org/"}],"subitem_relation_type_id":{"subitem_relation_type_id_text":"http://www.iop.org/","subitem_relation_type_select":"URI"}}]},"item_21_rights_13":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"Copyright (c) 2000 IOP Publishing Ltd"}]},"item_21_select_59":{"attribute_name":"査読の有無","attribute_value_mlt":[{"subitem_select_item":"yes"}]},"item_21_source_id_8":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"0957-4484","subitem_source_identifier_type":"ISSN"},{"subitem_source_identifier":"1361-6528","subitem_source_identifier_type":"ISSN"}]},"item_21_text_36":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Texas Instruments Japan Limited, Tokyo, Japan."},{"subitem_text_value":"Faculty of Engineering, Hiroshima University, 1-4-1, Kagamiyama, Higashi-Hiroshima, 739-8527, Japan (Kyushu Institute of Technology, Fukuoka, Japan)"},{"subitem_text_value":"Faculty of Engineering, Hiroshima University, 1-4-1, Kagamiyama, Higashi-Hiroshima, 739-8527, Japan"},{"subitem_text_value":"Faculty of Engineering, Hiroshima University, 1-4-1, Kagamiyama, Higashi-Hiroshima, 739-8527, Japan"}]},"item_21_version_type_58":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_ab4af688f83e57aa","subitem_version_type":"AM"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yamanaka, T"}],"nameIdentifiers":[{}]},{"creatorAffiliations":[{"affiliationNameIdentifiers":[],"affiliationNames":[{"affiliationName":""}]}],"creatorNames":[{"creatorName":"Morie, Takashi","creatorNameLang":"en"},{"creatorName":"森江, 隆","creatorNameLang":"ja"},{"creatorName":"モリエ, タカシ","creatorNameLang":"ja-Kana"}],"familyNames":[{},{},{}],"givenNames":[{},{},{}],"nameIdentifiers":[{},{},{},{}]},{"creatorNames":[{"creatorName":"Nagata, M"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Iwata, A"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2007-12-26"}],"displaytype":"detail","filename":"yamanaka00-nano.pdf","filesize":[{"value":"385.1 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"yamanaka00-nano.pdf","url":"https://kyutech.repo.nii.ac.jp/record/325/files/yamanaka00-nano.pdf"},"version_id":"82c4162e-028b-495c-b1c1-f4bba65f8396"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"A single-electron stochastic associative processing circuit robust to random background-charge effects and its structure using nanocrystal floating-gate transistors","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"A single-electron stochastic associative processing circuit robust to random background-charge effects and its structure using nanocrystal floating-gate transistors"}]},"item_type_id":"21","owner":"3","path":["24"],"pubdate":{"attribute_name":"公開日","attribute_value":"2007-12-26"},"publish_date":"2007-12-26","publish_status":"0","recid":"325","relation_version_is_last":true,"title":["A single-electron stochastic associative processing circuit robust to random background-charge effects and its structure using nanocrystal floating-gate transistors"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2023-10-25T10:55:58.517974+00:00"}