{"created":"2023-05-15T11:57:41.379402+00:00","id":3414,"links":{},"metadata":{"_buckets":{"deposit":"f42329bf-2d8b-4e2c-9310-60e45d331887"},"_deposit":{"created_by":14,"id":"3414","owners":[14],"pid":{"revision_id":0,"type":"depid","value":"3414"},"status":"published"},"_oai":{"id":"oai:kyutech.repo.nii.ac.jp:00003414","sets":["8:24"]},"author_link":["13692","1615","13694"],"item_21_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2009-07-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"7","bibliographicPageEnd":"1698","bibliographicPageStart":"1690","bibliographicVolumeNumber":"E92-A","bibliographic_titles":[{"bibliographic_title":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences","bibliographic_titleLang":"en"}]}]},"item_21_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"In this paper, we propose an analog CMOS circuit which achieves spiking neural networks with spike-timing dependent synaptic plasticity (STDP). In particular, we propose a STDP circuit with symmetric function for the first time, and also we demonstrate associative memory operation in a Hopfield-type feedback network with STDP learning. In our spiking neuron model, analog information expressing processing results is given by the relative timing of spike firing events. It is well known that a biological neuron changes its synaptic weights by STDP, which provides learning rules depending on relative timing between asynchronous spikes. Therefore, STDP can be used for spiking neural systems with learning function. The measurement results of fabricated chips using TSMC 0.25 µm CMOS process technology demonstrate that our spiking neuron circuit can construct feedback networks and update synaptic weights based on relative timing between asynchronous spikes by a symmetric or an asymmetric STDP circuits.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_21_description_60":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"subitem_description":"Journal Article","subitem_description_type":"Other"}]},"item_21_publisher_7":{"attribute_name":"出版社","attribute_value_mlt":[{"subitem_publisher":"電子情報通信学会","subitem_publisher_language":"ja"}]},"item_21_relation_12":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"https://doi.org/10.1587/transfun.E92.A.1690","subitem_relation_type_select":"DOI"}}]},"item_21_rights_13":{"attribute_name":"著作権関連情報","attribute_value_mlt":[{"subitem_rights":"Copyright (c) 2009 The Institute of Electronics, Information and Communication Engineers"}]},"item_21_select_59":{"attribute_name":"査読の有無","attribute_value_mlt":[{"subitem_select_item":"yes"}]},"item_21_source_id_10":{"attribute_name":"NCID","attribute_value_mlt":[{"subitem_source_identifier":"AA10826261","subitem_source_identifier_type":"NCID"}]},"item_21_source_id_8":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"0916-8516","subitem_source_identifier_type":"PISSN"},{"subitem_source_identifier":"1745-1345","subitem_source_identifier_type":"EISSN"}]},"item_21_text_64":{"attribute_name":"業績ID","attribute_value_mlt":[{"subitem_text_value":"97587155B018799249257688003A5ACA"}]},"item_21_version_type_58":{"attribute_name":"出版タイプ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tanaka, Hideki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorAffiliations":[{"affiliationNames":[{}]}],"creatorNames":[{"creatorName":"Morie, Takashi","creatorNameLang":"en"},{"creatorName":"森江, 隆","creatorNameLang":"ja"},{"creatorName":"モリエ, タカシ","creatorNameLang":"ja-Kana"}],"familyNames":[{},{},{}],"givenNames":[{},{},{}],"nameIdentifiers":[{},{},{},{}]},{"creatorNames":[{"creatorName":"Aihara, Kazuyuki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2010-02-05"}],"displaytype":"detail","filename":"CMOS09-ieice.pdf","filesize":[{"value":"919.2 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"CMOS09-ieice.pdf","url":"https://kyutech.repo.nii.ac.jp/record/3414/files/CMOS09-ieice.pdf"},"version_id":"91e97426-276e-4b79-a24a-af0161fe3b6e"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"spiking neuron model","subitem_subject_scheme":"Other"},{"subitem_subject":"associative memory","subitem_subject_scheme":"Other"},{"subitem_subject":"spike-timing dependent synaptic plasticity (STDP)","subitem_subject_scheme":"Other"},{"subitem_subject":"LSI implementation","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function","subitem_title_language":"en"}]},"item_type_id":"21","owner":"14","path":["24"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2010-02-05"},"publish_date":"2010-02-05","publish_status":"0","recid":"3414","relation_version_is_last":true,"title":["A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function"],"weko_creator_id":"14","weko_shared_id":-1},"updated":"2023-12-05T03:02:27.661003+00:00"}