Development and Qualification of an FPGA-Based Multi-Processor System-on-Chip On-Board Computer for LEO Satellites

Mohamed, Mahmoud Mohamed Ibrahim

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低軌道衛星のためのFPGAを用いたマルチプロセッサシステムの開発と検証

https://doi.org/10.18997/00004098

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D-234_kou_k_374.pdf (20.0 MB)

アイテムタイプ

学位論文 = Thesis or Dissertation(1)

公開日

2014-12-03

資源タイプ

資源タイプ識別子

http://purl.org/coar/resource_type/c_db06

資源タイプ

doctoral thesis

タイトル

Development and Qualification of an FPGA-Based Multi-Processor System-on-Chip On-Board Computer for LEO Satellites

言語

タイトル

低軌道衛星のためのFPGAを用いたマルチプロセッサシステムの開発と検証

言語

eng

著者

Mohamed, Mahmoud Mohamed Ibrahim

抄録

内容記述タイプ

Abstract

内容記述

Developing small satellites for scientific and commercial purposes is emerging rapidly in the last decade. The future is still expected to carry more challenging services and designs to fulfill the growing needs for space based services. Nevertheless, there exists a big challenge in developing cost effective and highly efficient small satellites yet with accepted reliability and power consumption that is adequate to the mission capabilities. This challenge mandates the use of the recent developments in digital design techniques and technologies to strike the required balance between the four basic parameters: 1） Cost, 2） Performance, 3） Reliability and 4） Power consumption. This balance becomes even more stringent and harder toreach when the satellite mass reduces significantly. Mass reduction puts strict constraints on the power system in terms of the solar panels and the batteries. That fact creates the need to miniaturize the design of the subsystems as much as possible which can be viewed as the fifth parameter in the design balance dilemma.
At Kyuhsu Institute of Technology-Japan we are investigating the use of SRAMbased Field Programmable Gate Arrays （FPGA） in building: 1） High performance, 2）Low cost, 3） Moderate power consumption and 4） Highly reliable Muti-Processor System-on-Chip （MPSoC） On-Board Computers （OBC） for future space missions and applications. This research tries to investigate how commercial grade SRAMbased FPGAs would perform in space and how to mitigate them against the space environment. Our methodology to answer that question depended on following formal design procedure for the OBC according to the space environment requirements then qualifying the design through extensive testing. We developed theMPSoC OBC with 4 complete embedded processor systems. The Inter Processor Communication （IPC） takes place through hardware First-In-First-Out （FIFO） mailboxes. One processor acts as the system master controller which monitors the operation and controls the reset and restore of the system in case of faults and the other three processors form Triple Modular Redundancy （TMR） fault tolerance architecture with each other. We used Dynamic Partial Reconfiguration （DPR） in scrubbing the configuration memory frames and correcting the faults that might exist. The system is implemented using a Virtex-5 LX50 commercial grade FPGA from Xilinx. The research also qualifies the design in the ground-simulated space environment conditions. We tested the implemented MPSoC OBC in Thermal Vacuum Chambers （TVC） at the Center of Nano-Satellite Testing （CeNT） at Kyushu Institute of Technology. Also we irradiated the design with proton accelerated beam at 65 MeV with fluxes of 10e06 and 3e06 particle/cm2/sec at the Takasaki Advanced Radiation Research Institute （TARRI）.
The TVC test results showed that the FPGA design exceeded the limits of normal operation for the commercial grade package at about 105 C°. Therefore, we mitigated the package using: 1） heat sink, 2） dynamic temperature management through operating frequency reduction from 100 MHz to 50 MHz and 3） reconfiguration to reduce the number of working processors to 2 instead of 4 by replacing the spaceredundancy TMR with time-redundancy TMR during the sunlight section of the orbit. The mitigation proved to be efficient and it even reduced the temperature from 105 C° to about 66 C° when the heat sink, frequency reduction, and reconfiguration techniques were used together.
The radiation and the fault injection tests showed that mitigating the FPGA configuration frames through scrubbing are efficient when Single Bit Upsets （SBU） are recorded. Multiple Bit Upsets （MBU） are not well mitigated using the scrubbing with Single Error Correction Double Error Detection （SECDED） technique and the FPGA needs to be totally reset and reloaded when MBUs are detected in its configuration frames. However, as MBUs occurrence in space is very seldom and rare compared to SBUs, we consider that SECDED scrubbing is very efficient in decreasing the soft error rate and increasing the reliability of having error-free bitstreams. The reliability was proven to be at 0.9999 when the scrubbing rate was continuous at a period of 7.1 msec between complete scans of the FPGA bitstream. In the proton radiation tests we managed to develop a new technique to estimate the static cross section using internal scrubbing only without using external monitoring, control and scrubbing device. Fault injection was used to estimate the dynamic cross section in a cost effective alternative for estimating it through radiation test.
The research proved through detailed testing that the 65 nm commercial grade SRAM-based FPGA can be used in future space missions. The MPSoC OBC design achieved an adequate balance between the performance, power, mass, and reliability requirements. Extensive testing and applying carefully crafted mitigation techniques were the key points to verify and validate the MPSoC OBC design. In-orbit validation through a scientific demonstration mission would be the next step for the future research.

言語

内容記述タイプ

TableOfContents

内容記述

Chapter 1: Introduction||Chapter 2: Background and Literature Review||Chapter 3: Multi-Processor System-on-Chip On-Borad Computer Design||Chapter 4: Space and Time Redundancy Trade-offs||Chapter 5: Radiation and Fault Injection Testing||Chapter 6: Thermal Vacuum Testing||Chapter 7: Results and Discussion||Chapter 8: Conclusion and Future Perspectives||References

備考

内容記述タイプ

Other

内容記述

九州工業大学博士学位論文学位記番号:工博甲第374号　学位授与年月日:平成26年9月26日

キーワード

主題Scheme

Other

主題

Fault Tolerant System

キーワード

主題Scheme

Other

主題

MPSoC

キーワード

主題Scheme

Other

主題

On-Board Computer

キーワード

主題Scheme

Other

主題

LEO Satellites

キーワード

主題Scheme

Other

主題

Environmental Test

キーワード

主題Scheme

Other

主題

Space Development

アドバイザー

浅海, 賢一

学位授与番号

甲第374号

学位名

博士（工学）

学位授与年月日

2014-09-26

学位授与機関

学位授与機関識別子Scheme

kakenhi

学位授与機関識別子

17104

学位授与機関名

九州工業大学

学位授与年度

内容記述タイプ

Other

内容記述

平成26年度

出版タイプ

VoR

出版タイプResource

http://purl.org/coar/version/c_970fb48d4fbd8a85

アクセス権

open access

アクセス権URI

http://purl.org/coar/access_right/c_abf2

ID登録

10.18997/00004098

ID登録タイプ

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低軌道衛星のためのFPGAを用いたマルチプロセッサシステムの開発と検証

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