@inproceedings{oai:kyutech.repo.nii.ac.jp:00004459,
 author = {Miyase, Kohei and 宮瀬, 紘平 and Uchinodan, Y. and Enokimoto, K. and Yamato, Y. and Wen, Xiaoqing and 温, 暁青 and Kajihara, Seiji and 梶原, 誠司 and Wu, F. and Dilillo, L. and Bosio, A. and Girard, P. and Virazel, A.},
 book = {20th Asian test symposium : (ATS 2011) : New Delhi, India : 20-23 November 2011},
 month = {Nov},
 note = {It has become necessary to reduce power during LSI testing. Particularly, during at-speed testing, excessive power consumed during the Launch-To-Capture (LTC) cycle causes serious issues that may lead to the overkill of defect-free logic ICs. Many successful test generation approaches to reduce IR-drop and/or power supply noise during LTC for the launch-off capture (LOC) scheme have previously been proposed, and several of X-filling techniques have proven especially effective. With X-filling in the launch-off shift (LOS) scheme, however, adjacent-fill (which was originally proposed for shift-in power reduction) is used frequently. In this work, we propose a novel X-filling technique for the LOS scheme, called Adjacent-Probability-based X-Filling (AP-fill), which can reduce more LTC power than adjacent-fill. We incorporate AP-fill into a post-ATPG test modification flow consisting of test relaxation and X-filling in order to avoid the fault coverage loss and the test vector count inflation. Experimental results for larger ITC'99 circuits show that the proposed AP-fill technique can achieve a higher power reduction ratio than 0-fill, 1-fill, and adjacent-fill., 2011 Asian Test Symposium, 20-23 November 2011, New Delhi, India},
 pages = {90--95},
 publisher = {IEEE},
 title = {Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling},
 volume = {2011},
 year = {2011},
 yomi = {ミヤセ, コウヘイ and オン, ギョウセイ and カジハラ, セイジ}
}