@inproceedings{oai:kyutech.repo.nii.ac.jp:00005044,
 author = {Wang, Senling and Sato, Yasuo and Miyase, Kohei and 宮瀬, 紘平 and Kajihara, Seiji and 梶原, 誠司},
 book = {2012 IEEE 21st Asian Test Symposium},
 month = {Dec},
 note = {High test power in logic BIST is a serious problem not only for production test, but also for board test, system debug or field test. Many low power BIST approaches that focus on scan-shift power or capture power have been proposed. However, it is known that a half of scan-shift power is compensated by test responses, which is difficult to control in those approaches. This paper proposes a novel approach that directly reduces scan-out power by modifying some flip-flops' values in scan chains at the last capture. Experimental results show that the proposed method reduces scan-out power up to 30% with little loss of test coverage., 2012 IEEE 21st Asian Test Symposium, 19-22 Nov. 2012, Niigata, Japan},
 pages = {272--277},
 publisher = {IEEE},
 title = {A Scan-Out Power Reduction Method for Multi-Cycle BIST},
 year = {2012},
 yomi = {ミヤセ, コウヘイ and カジハラ, セイジ}
}