@article{oai:kyutech.repo.nii.ac.jp:00006314,
 author = {Ni, Tianming and Nie, Mu and Liang, Huaguo and Bian, Jingchang and Xu, Xiumin and Fang, Xiangsheng and Huang, Zhengfeng and Wen, Xiaoqing and 温, 暁青},
 issue = {18},
 journal = {IEICE Electronics Express},
 month = {Sep},
 note = {Defects in TSV will lead to variations in the propagation delay of the net connected to the faulty TSV. A non-invasive Vernier Ring based method for TSV pre-bond testing is proposed to detect resistive open and leakage faults. TSVs are used as capacitive loads of their driving gates, then time interval compared with the fault-free TSVs will be detected. The time interval can be detected with picosecond level resolution, and digitized into a digital code to compare with an expected value of fault-free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of time interval 10 ps, resistive open defects 0.2 kΩ above and equivalent leakage resistance less than 18 MΩ. Compared with existing methods, detection precision, area overhead, and test time are effectively improved, furthermore, the fault degree can be digitalized into digital code.},
 pages = {20170590-1--20170590-11},
 title = {Vernier ring based pre-bond through silicon vias test in 3D ICs},
 volume = {14},
 year = {2017},
 yomi = {オン, ギョウセイ}
}