@article{oai:kyutech.repo.nii.ac.jp:00006317,
 author = {Tomita, Akihiro and Wen, Xiaoqing and 温, 暁青 and Sato, Yasuo and Kajihara, Seiji and 梶原, 誠司 and Miyase, Kohei and 宮瀬, 紘平 and Holst, Stefan and ホルスト, シュテファン and Girard, Patrick and Tehranipoor, Mohammad and Wang, Laung-Terng},
 issue = {10},
 journal = {IEICE Transactions on Information and Systems},
 month = {Oct},
 note = {The applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses even for good circuits. Different from conventional low-power BIST, this paper is the first to explicitly focus on achieving capture power safety with a novel and practical scheme, called capture-power-safe logic BIST (CPS-LBIST). The basic idea is to identify all possibly-erroneous test responses caused by excessive capture power and use the well-known approach of masking (bit-masking, slice-masking, vector-masking) to block them from reaching the multiple-input signature register (MISR). Experiments with large benchmark circuits and a large industrial circuit demonstrate that CPS-LBIST can achieve capture power safety with negligible impact on test quality and circuit overhead.},
 pages = {2706--2718},
 title = {On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST},
 volume = {E97.D},
 year = {2014},
 yomi = {オン, ギョウセイ and カジハラ, セイジ and ミヤセ, コウヘイ}
}