{"created":"2023-05-15T11:59:44.642947+00:00","id":6317,"links":{},"metadata":{"_buckets":{"deposit":"2b2f506a-2382-4b82-b792-d07c0a28fc4b"},"_deposit":{"created_by":3,"id":"6317","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"6317"},"status":"published"},"_oai":{"id":"oai:kyutech.repo.nii.ac.jp:00006317","sets":["8:24"]},"author_link":["26082","1143","26084","1147","6567","26087","26088","26089","26090"],"control_number":"6317","item_1689815586683":{"attribute_name":"CRID","attribute_value_mlt":[{"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"https://cir.nii.ac.jp/crid/1390282679355372672","subitem_relation_type_select":"URI"}}]},"item_21_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2014-10-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"10","bibliographicPageEnd":"2718","bibliographicPageStart":"2706","bibliographicVolumeNumber":"E97.D","bibliographic_titles":[{"bibliographic_title":"IEICE Transactions on Information and Systems","bibliographic_titleLang":"en"}]}]},"item_21_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"The applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses even for good circuits. Different from conventional low-power BIST, this paper is the first to explicitly focus on achieving capture power safety with a novel and practical scheme, called capture-power-safe logic BIST (CPS-LBIST). The basic idea is to identify all possibly-erroneous test responses caused by excessive capture power and use the well-known approach of masking (bit-masking, slice-masking, vector-masking) to block them from reaching the multiple-input signature register (MISR). Experiments with large benchmark circuits and a large industrial circuit demonstrate that CPS-LBIST can achieve capture power safety with negligible impact on test quality and circuit overhead.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_21_link_62":{"attribute_name":"研究者情報","attribute_value_mlt":[{"subitem_link_url":"https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html"}]},"item_21_publisher_7":{"attribute_name":"出版社","attribute_value_mlt":[{"subitem_publisher":"電子情報通信学会","subitem_publisher_language":"ja"}]},"item_21_relation_12":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"https://doi.org/10.1587/transinf.2014EDP7039","subitem_relation_type_select":"DOI"}}]},"item_21_rights_13":{"attribute_name":"著作権関連情報","attribute_value_mlt":[{"subitem_rights":"Copyright (c) 2014 The Institute of Electronics, Information and Communication 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BIST","subitem_subject_scheme":"Other"},{"subitem_subject":"capture power safety","subitem_subject_scheme":"Other"},{"subitem_subject":"masking","subitem_subject_scheme":"Other"},{"subitem_subject":"IR-drop","subitem_subject_scheme":"Other"},{"subitem_subject":"transition delay fault","subitem_subject_scheme":"Other"},{"subitem_subject":"long sensitized path","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"On Achieving Capture Power Safety in At-Speed Scan-Based Logic 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