@article{oai:kyutech.repo.nii.ac.jp:00006320,
 author = {Miyase, Kohei and 宮瀬, 紘平 and Wen, Xiaoqing and 温, 暁青 and Furukawa, Hiroshi and Yamato, Yuta and Kajihara, Seiji and 梶原, 誠司 and Girard, Patrick and Wang, Laung-Terng and Tehranipoor, Mohammad},
 issue = {1},
 journal = {IEICE Transactions on Information and Systems},
 month = {Jan},
 note = {At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to equalize the input and output values in Stage-2of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design.},
 pages = {2--9},
 title = {High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme},
 volume = {E93.D},
 year = {2010},
 yomi = {ミヤセ, コウヘイ and オン, ギョウセイ and カジハラ, セイジ}
}