{"created":"2023-05-15T11:59:44.771969+00:00","id":6320,"links":{},"metadata":{"_buckets":{"deposit":"43e8c2da-373e-40ff-820e-50d6487f3b3c"},"_deposit":{"created_by":3,"id":"6320","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"6320"},"status":"published"},"_oai":{"id":"oai:kyutech.repo.nii.ac.jp:00006320","sets":["8:24"]},"author_link":["6567","1143","26122","26123","1147","26125","26126","26127"],"control_number":"6320","item_1689815586683":{"attribute_name":"CRID","attribute_value_mlt":[{"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"https://cir.nii.ac.jp/crid/1390001204378865152","subitem_relation_type_select":"URI"}}]},"item_21_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2010-01-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1","bibliographicPageEnd":"9","bibliographicPageStart":"2","bibliographicVolumeNumber":"E93.D","bibliographic_titles":[{"bibliographic_title":"IEICE Transactions on Information and Systems","bibliographic_titleLang":"en"}]}]},"item_21_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to equalize the input and output values in Stage-2of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_21_link_62":{"attribute_name":"研究者情報","attribute_value_mlt":[{"subitem_link_url":"https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html"}]},"item_21_publisher_7":{"attribute_name":"出版社","attribute_value_mlt":[{"subitem_publisher":"電子情報通信学会","subitem_publisher_language":"ja"}]},"item_21_relation_12":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"https://doi.org/10.1587/transinf.E93.D.2","subitem_relation_type_select":"DOI"}}]},"item_21_rights_13":{"attribute_name":"著作権関連情報","attribute_value_mlt":[{"subitem_rights":"Copyright (c) 2010 The Institute of Electronics, Information and Communication Engineers"}]},"item_21_select_59":{"attribute_name":"査読の有無","attribute_value_mlt":[{"subitem_select_item":"yes"}]},"item_21_source_id_10":{"attribute_name":"NCID","attribute_value_mlt":[{"subitem_source_identifier":"AA10826272","subitem_source_identifier_type":"NCID"}]},"item_21_source_id_8":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1745-1361","subitem_source_identifier_type":"EISSN"},{"subitem_source_identifier":"0916-8532","subitem_source_identifier_type":"PISSN"}]},"item_21_subject_16":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"549","subitem_subject_scheme":"NDC"}]},"item_21_text_28":{"attribute_name":"論文ID（連携）","attribute_value_mlt":[{"subitem_text_value":"10302941"}]},"item_21_text_63":{"attribute_name":"連携ID","attribute_value_mlt":[{"subitem_text_value":"8039"}]},"item_21_version_type_58":{"attribute_name":"出版タイプ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorAffiliations":[{"affiliationNames":[{}]}],"creatorNames":[{"creatorName":"Miyase, Kohei","creatorNameLang":"en"},{"creatorName":"宮瀬, 紘平","creatorNameLang":"ja"},{"creatorName":"ミヤセ, コウヘイ","creatorNameLang":"ja-Kana"}],"familyNames":[{},{},{}],"givenNames":[{},{},{}],"nameIdentifiers":[{},{},{},{}]},{"creatorAffiliations":[{"affiliationNames":[{}]}],"creatorNames":[{"creatorName":"Wen, Xiaoqing","creatorNameLang":"en"},{"creatorName":"温, 暁青","creatorNameLang":"ja"},{"creatorName":"オン, ギョウセイ","creatorNameLang":"ja-Kana"}],"familyNames":[{},{},{}],"givenNames":[{},{},{}],"nameIdentifiers":[{},{},{},{}]},{"creatorAlternatives":[{"creatorAlternative":"Furukawa, H.","creatorAlternativeLang":"en"}],"creatorNames":[{"creatorName":"Furukawa, Hiroshi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorAlternatives":[{"creatorAlternative":"Yamato, Y.","creatorAlternativeLang":"en"}],"creatorNames":[{"creatorName":"Yamato, Yuta","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorAffiliations":[{"affiliationNames":[{}]}],"creatorNames":[{"creatorName":"Kajihara, Seiji","creatorNameLang":"en"},{"creatorName":"梶原, 誠司","creatorNameLang":"ja"},{"creatorName":"カジハラ, セイジ","creatorNameLang":"ja-Kana"}],"familyNames":[{},{},{}],"givenNames":[{},{},{}],"nameIdentifiers":[{},{},{},{}]},{"creatorAlternatives":[{"creatorAlternative":"Girard, P.","creatorAlternativeLang":"en"}],"creatorNames":[{"creatorName":"Girard, Patrick","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorAlternatives":[{"creatorAlternative":"Wang, L.","creatorAlternativeLang":"en"}],"creatorNames":[{"creatorName":"Wang, Laung-Terng","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorAlternatives":[{"creatorAlternative":"Tehranipoor, M.","creatorAlternativeLang":"en"}],"creatorNames":[{"creatorName":"Tehranipoor, Mohammad","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-01-15"}],"displaytype":"detail","filename":"transinf.E93.D.2.pdf","filesize":[{"value":"1.8 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"transinf.E93.D.2.pdf","url":"https://kyutech.repo.nii.ac.jp/record/6320/files/transinf.E93.D.2.pdf"},"version_id":"877aec13-8061-44c6-82dc-a6996dc1531f"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"power supply noise","subitem_subject_scheme":"Other"},{"subitem_subject":"test relaxation","subitem_subject_scheme":"Other"},{"subitem_subject":"X-filling","subitem_subject_scheme":"Other"},{"subitem_subject":"clock-gating","subitem_subject_scheme":"Other"},{"subitem_subject":"test compaction","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme","subitem_title_language":"en"}]},"item_type_id":"21","owner":"3","path":["24"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2020-01-15"},"publish_date":"2020-01-15","publish_status":"0","recid":"6320","relation_version_is_last":true,"title":["High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme"],"weko_creator_id":"3","weko_shared_id":-1},"updated":"2024-01-26T05:59:11.831869+00:00"}