@article{oai:kyutech.repo.nii.ac.jp:00006324,
 author = {Oku, Shinji and Kajihara, Seiji and 梶原, 誠司 and Sato, Yasuo and Miyase, Kohei and 宮瀬, 紘平 and Wen, Xiaoqing and 温, 暁青},
 journal = {IPSJ Transactions on System LSI Design Methodology},
 month = {Aug},
 note = {This paper proposes a method to compute delay values in 3-valued fault simulation for test cubes which are test patterns with unspecified values (Xs). Because the detectable delay size of each fault by a test cube is not fixed before assigning logic values to the Xs in the test cube, the proposed method only computes a range of the detectable delay values of the test patterns covered by the test cubes. By using the proposed method, we derive the lowest and the highest test quality of test patterns covered by the test cubes. Furthermore, we also propose a GA (genetic algorithm)-based method to generate fully specified test patterns with high test quality from test cubes. Experimental results for benchmark circuits show the effectiveness of the proposed methods.},
 pages = {283--291},
 title = {On Delay Test Quality for Test Cubes},
 volume = {3},
 year = {2010},
 yomi = {カジハラ, セイジ and ミヤセ, コウヘイ and オン, ギョウセイ}
}