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A Ratio-Less 10-Transistor Cell and Static Column Retention Loop Structure for Fully Digital SRAM
http://hdl.handle.net/10228/00007544
http://hdl.handle.net/10228/0000754458aa6543-7495-49d4-9e12-12f46544803f
| 名前 / ファイル | ライセンス | アクション |
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10245958.pdf (601.1 kB)
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| アイテムタイプ | 会議発表論文 = Conference Paper(1) | |||||||||||
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| 公開日 | 2020-01-20 | |||||||||||
| 資源タイプ | ||||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||||||||
| 資源タイプ | conference paper | |||||||||||
| タイトル | ||||||||||||
| タイトル | A Ratio-Less 10-Transistor Cell and Static Column Retention Loop Structure for Fully Digital SRAM | |||||||||||
| 言語 | en | |||||||||||
| 言語 | ||||||||||||
| 言語 | eng | |||||||||||
| 著者 |
Saito, Takahiko
× Saito, Takahiko× Okamura, Hitoshi× Yamamoto, Hiromasa× 中村, 和之
WEKO
26231
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| 抄録 | ||||||||||||
| 内容記述タイプ | Abstract | |||||||||||
| 内容記述 | In this paper, a new memory cell along with a new peripheral circuit for SRAM in ultra fine advanced process technologies is presented. A unique feature of the proposed circuit technique is its circuit design concept to achieve the fully digital ratio-less operation. This enables memory cell design that is free from consideration of the Static Noise Margin (SNM). Furthermore, it enables SRAM function without the restriction of transistor parameter (W/L) settings in circuit design and the dependency on local process variation. To achieve these unique features, we propose (1) a ratio-less memory cell in which the flip/flop loop can be broken in write operation and a push-pull tri-state buffer for secure read operation and (2) the configuration of a static Column Retention Loop (CRL) to prevent loss of memory cell data in the write half-select state. Combining these two key circuit techniques, a new SRAM circuit that is free from design restriction of SNM was developed. A 0.18-μm 1024-bit MOSAIC SRAM TEG consisting of memory cells having all combinations of gate sizes of 10 transistors differing by two orders of magnitude was developed and tested to verify the proposed circuits. | |||||||||||
| 言語 | en | |||||||||||
| 備考 | ||||||||||||
| 内容記述タイプ | Other | |||||||||||
| 内容記述 | 4th IEEE International Memory Workshop (IMW 2012), 20-23 May 2012, Milan, Italy | |||||||||||
| 書誌情報 |
en : 2012 4th IEEE International Memory Workshop 発行日 2012-06-11 |
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| 出版社 | ||||||||||||
| 出版社 | IEEE | |||||||||||
| DOI | ||||||||||||
| 関連タイプ | isVersionOf | |||||||||||
| 識別子タイプ | DOI | |||||||||||
| 関連識別子 | https://doi.org/10.1109/IMW.2012.6213677 | |||||||||||
| ISBN | ||||||||||||
| 識別子タイプ | ISBN | |||||||||||
| 関連識別子 | 978-1-4673-1081-9 | |||||||||||
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| 識別子タイプ | ISBN | |||||||||||
| 関連識別子 | 978-1-4673-1079-6 | |||||||||||
| ISSN | ||||||||||||
| 収録物識別子タイプ | EISSN | |||||||||||
| 収録物識別子 | 2159-4864 | |||||||||||
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| 収録物識別子タイプ | PISSN | |||||||||||
| 収録物識別子 | 2159-483X | |||||||||||
| 著作権関連情報 | ||||||||||||
| 権利情報 | Copyright (c) 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||||||||
| キーワード | ||||||||||||
| 主題Scheme | Other | |||||||||||
| 主題 | Random access memory | |||||||||||
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| 主題Scheme | Other | |||||||||||
| 主題 | Transistors | |||||||||||
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| 主題Scheme | Other | |||||||||||
| 主題 | Wireless sensor networks | |||||||||||
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| 主題Scheme | Other | |||||||||||
| 主題 | Inverters | |||||||||||
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| 主題Scheme | Other | |||||||||||
| 主題 | Logic gates | |||||||||||
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| 主題Scheme | Other | |||||||||||
| 主題 | Registers | |||||||||||
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| 主題Scheme | Other | |||||||||||
| 主題 | CMOS integrated circuits | |||||||||||
| 出版タイプ | ||||||||||||
| 出版タイプ | AM | |||||||||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||||||||
| 査読の有無 | ||||||||||||
| 値 | yes | |||||||||||
| 研究者情報 | ||||||||||||
| URL | https://hyokadb02.jimu.kyutech.ac.jp/html/381_ja.html | |||||||||||
| 論文ID（連携） | ||||||||||||
| 値 | 10245958 | |||||||||||
| 連携ID | ||||||||||||
| 値 | 8051 | |||||||||||
