@inproceedings{oai:kyutech.repo.nii.ac.jp:00006336,
 author = {Hirakawa, Yutaka and Motomura, Ayami and Ota, Kohei and Mimura, Norihiro and Nakamura, Kazuyuki and 中村, 和之},
 book = {2012 IEEE International Conference on Microelectronic Test Structures (ICMTS)},
 month = {Apr},
 note = {To validate our optimized design theory for Even Stage Ring Oscillators (ESROs), we have developed a Universal ESRO TEG (U-ESRO TEG) constructed with Equivalent Variable-W Transistors (EVWTs) and Initial-voltage Preset-able Inverters (IPIs). The design parameters can be changed with a single circuit, and it is possible to measure the operation margin and oscillation availability of an ESRO. Experimental results confirm the validity of our ESRO design theory., IEEE International Conference on Microelectronic Test Structures (ICMTS 2012), 19-22 March 2012, San Diego, CA, USA},
 publisher = {IEEE},
 title = {A universal test structure for the direct measurement of the design margin of even-stage ring oscillators with CMOS latch},
 year = {2012},
 yomi = {ナカムラ, カズユキ}
}