{"created":"2023-05-15T11:59:45.441844+00:00","id":6336,"links":{},"metadata":{"_buckets":{"deposit":"fe574f5c-12a6-4867-9106-439ff5a87a1a"},"_deposit":{"created_by":3,"id":"6336","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"6336"},"status":"published"},"_oai":{"id":"oai:kyutech.repo.nii.ac.jp:00006336","sets":["15:20"]},"author_link":["26274","26275","26276","26277","26231"],"control_number":"6336","item_23_alternative_title_18":{"attribute_name":"その他のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"A Universal Test Structure for the Direct Measurement of the Design Margin of Even-Stage Ring Oscillators with CMOS Latch","subitem_alternative_title_language":"en"}]},"item_23_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2012-04-26","bibliographicIssueDateType":"Issued"},"bibliographic_titles":[{"bibliographic_title":"2012 IEEE International Conference on Microelectronic Test Structures (ICMTS)","bibliographic_titleLang":"en"}]}]},"item_23_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"To validate our optimized design theory for Even Stage Ring Oscillators (ESROs), we have developed a Universal ESRO TEG (U-ESRO TEG) constructed with Equivalent Variable-W Transistors (EVWTs) and Initial-voltage Preset-able Inverters (IPIs). The design parameters can be changed with a single circuit, and it is possible to measure the operation margin and oscillation availability of an ESRO. Experimental results confirm the validity of our ESRO design theory.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_23_description_5":{"attribute_name":"備考","attribute_value_mlt":[{"subitem_description":"IEEE International Conference on Microelectronic Test Structures (ICMTS 2012), 19-22 March 2012, San Diego, CA, USA","subitem_description_type":"Other"}]},"item_23_description_60":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"subitem_description":"Conference Paper","subitem_description_type":"Other"}]},"item_23_link_61":{"attribute_name":"研究者情報","attribute_value_mlt":[{"subitem_link_url":"https://hyokadb02.jimu.kyutech.ac.jp/html/381_ja.html"}]},"item_23_publisher_7":{"attribute_name":"出版社","attribute_value_mlt":[{"subitem_publisher":"IEEE"}]},"item_23_relation_12":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"https://doi.org/10.1109/ICMTS.2012.6190605","subitem_relation_type_select":"DOI"}}]},"item_23_relation_9":{"attribute_name":"ISBN","attribute_value_mlt":[{"subitem_relation_type_id":{"subitem_relation_type_id_text":"978-1-4673-1030-7","subitem_relation_type_select":"ISBN"}},{"subitem_relation_type_id":{"subitem_relation_type_id_text":"978-1-4673-1027-7","subitem_relation_type_select":"ISBN"}},{"subitem_relation_type_id":{"subitem_relation_type_id_text":"978-1-4673-1029-1","subitem_relation_type_select":"ISBN"}}]},"item_23_rights_13":{"attribute_name":"著作権関連情報","attribute_value_mlt":[{"subitem_rights":"Copyright (c)  2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works."}]},"item_23_select_59":{"attribute_name":"査読の有無","attribute_value_mlt":[{"subitem_select_item":"yes"}]},"item_23_source_id_8":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2158-1029","subitem_source_identifier_type":"EISSN"},{"subitem_source_identifier":"1071-9032","subitem_source_identifier_type":"PISSN"}]},"item_23_text_28":{"attribute_name":"論文ID（連携）","attribute_value_mlt":[{"subitem_text_value":"10229125"}]},"item_23_text_62":{"attribute_name":"連携ID","attribute_value_mlt":[{"subitem_text_value":"8055"}]},"item_23_version_type_58":{"attribute_name":"出版タイプ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_ab4af688f83e57aa","subitem_version_type":"AM"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorAlternatives":[{}],"creatorNames":[{"creatorName":"Hirakawa, Yutaka","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorAlternatives":[{}],"creatorNames":[{"creatorName":"Motomura, Ayami","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorAlternatives":[{}],"creatorNames":[{"creatorName":"Ota, Kohei","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorAlternatives":[{}],"creatorNames":[{"creatorName":"Mimura, Norihiro","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorAffiliations":[{"affiliationNames":[{"affiliationNameLang":"ja"}]}],"creatorNames":[{"creatorName":"Nakamura, Kazuyuki","creatorNameLang":"en"},{"creatorName":"中村, 和之","creatorNameLang":"ja"},{"creatorName":"ナカムラ, カズユキ","creatorNameLang":"ja-Kana"}],"familyNames":[{},{},{}],"givenNames":[{},{},{}],"nameIdentifiers":[{},{},{},{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-01-21"}],"displaytype":"detail","filename":"10229125.pdf","filesize":[{"value":"598.2 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"10229125.pdf","url":"https://kyutech.repo.nii.ac.jp/record/6336/files/10229125.pdf"},"version_id":"4295600d-b6ef-4417-8074-0a274f947c4f"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Latches","subitem_subject_scheme":"Other"},{"subitem_subject":"Random access memory","subitem_subject_scheme":"Other"},{"subitem_subject":"Tin","subitem_subject_scheme":"Other"},{"subitem_subject":"Pins","subitem_subject_scheme":"Other"},{"subitem_subject":"CMOS integrated circuits","subitem_subject_scheme":"Other"},{"subitem_subject":"Inverters","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"conference paper","resourceuri":"http://purl.org/coar/resource_type/c_5794"}]},"item_title":"A universal test structure for the direct measurement of the design margin of even-stage ring oscillators with CMOS latch","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"A universal test structure for the direct measurement of the design margin of even-stage ring oscillators with CMOS latch","subitem_title_language":"en"}]},"item_type_id":"23","owner":"3","path":["20"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2020-01-21"},"publish_date":"2020-01-21","publish_status":"0","recid":"6336","relation_version_is_last":true,"title":["A universal test structure for the direct measurement of the design margin of even-stage ring oscillators with CMOS latch"],"weko_creator_id":"3","weko_shared_id":-1},"updated":"2024-01-31T07:32:24.377212+00:00"}