@inproceedings{oai:kyutech.repo.nii.ac.jp:00006337,
 author = {Okamura, Hitoshi and Saito, Takahiko and Goto, Hiroaki and Yamamoto, Masahiro and Nakamura, Kazuyuki and 中村, 和之},
 book = {2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)},
 month = {Jun},
 note = {MOSAIC SRAM Cell TEGs consisting of memory cells having all combinations of gate sizes of transistors differing by two orders of magnitude were developed with 0.18 μm CMOS process to verify the operation margins for SRAM circuits. The measured results show the operation of the ratio-less SRAM is completely independent of the size of transistors in the memory cell., IEEE International Conference on Microelectronic Test Structures (ICMTS 2013), 25-28 March 2013, Osaka, Japan},
 publisher = {IEEE},
 title = {Mosaic SRAM Cell TEGs with intentionally-added device variability for confirming the ratio-less SRAM operation},
 year = {2013},
 yomi = {ナカムラ, カズユキ}
}