@article{oai:kyutech.repo.nii.ac.jp:00006371,
 author = {Wen, Xiaoqing and 温, 暁青 and Yamashita,  Yoshiyuki and Kajihara, Seiji and 梶原, 誠司 and Wang,  Laung-Terng and Saluja,  Kewal K. and Kinoshita,  Kozo},
 journal = {23rd IEEE VLSI Test Symposium (VTS'05)},
 month = {Jun},
 note = {Research on low-power scan testing has been focused on the shift mode, with little or no consideration given to the capture mode power. However, high switching activity when capturing a test response can cause excessive IR drop, resulting in significant yield loss. This paper addresses this problem with a novel low-capture-power X-filling method by assigning 0's and 1's to unspecified (X) bits in a test cube to reduce the switching activity in capture mode. This method can be easily incorporated into any test generation flow, where test cubes are obtained during ATPG or by X-bit identification. Experimental results show the effectiveness of this method in reducing capture power dissipation without any impact on area, timing, and fault coverage., 23rd IEEE VLSI Test Symposium (VTS'05), 1-5 May 2005, Palm Springs, California, USA},
 pages = {265--270},
 title = {On Low-Capture-Power Test Generation for Scan Testing},
 year = {2005},
 yomi = {オン, ギョウセイ and カジハラ, セイジ}
}