@article{oai:kyutech.repo.nii.ac.jp:00006372,
 author = {Wen, Xiaoqing and 温, 暁青 and Kajihara, Seiji and 梶原, 誠司 and Miyase, Kohei and 宮瀬, 紘平 and Suzuki,  Tatsuya and Saluja,  Kewal K. and Wang,  Laung-Terng and Abdel-Hafez,  Khader S. and Kinoshita,  Kozo},
 journal = {24th IEEE VLSI Test Symposium},
 month = {May},
 note = {High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive JR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness, 24th IEEE VLSI Test Symposium (VTS'06), 30 April-4 May 2006, Berkeley, CA, USA},
 pages = {58--63},
 title = {A New ATPG Method for Efficient Capture Power Reduction During Scan Testing},
 year = {2006},
 yomi = {オン, ギョウセイ and カジハラ, セイジ and ミヤセ, コウヘイ}
}