@article{oai:kyutech.repo.nii.ac.jp:00006377,
 author = {Wen, Xiaoqing and 温, 暁青 and Miyase, Kohei and 宮瀬, 紘平 and Kajihara, Seiji and 梶原, 誠司 and Suzuki,  Tatsuya and Yamato,  Yuta and Girard,  Patrick and Ohsumi,  Yuji and Wang,  Laung-Terng},
 journal = {2007 IEEE International Test Conference},
 month = {Jan},
 note = {High-quality at-speed scan testing, characterized by high small-delay-defect detecting capability, is indispensable to achieve high delay test quality for DSM circuits. However, such testing is susceptible to yield loss due to excessive power supply noise caused by high launch-induced switching activity. This paper addresses this serious problem with a novel and practical post-ATPG X-filling scheme, featuring (1) a test relaxation method, called path keeping X-identification, that finds don't-care bits from a fully-specified transition delay test set while preserving its delay test quality by keeping the longest paths originally sensitized for fault detection, and (2) an X-filling method, called justification-probability-based fill (JP-fill), that is both effective and scalable for reducing launch-induced switching activity. This scheme can be easily implemented into any ATPG flow to effectively reduce power supply noise, without any impact on delay test quality, test data volume, area overhead, and circuit timing., 2007 IEEE International Test Conference, 21-26 October 2007, Santa Clara, CA, USA},
 title = {A novel scheme to reduce power supply noise for high-quality at-speed scan testing},
 year = {2008},
 yomi = {オン, ギョウセイ and ミヤセ, コウヘイ and カジハラ, セイジ}
}