@article{oai:kyutech.repo.nii.ac.jp:00006385,
 author = {Tomita,  A. and Wen, Xiaoqing and 温, 暁青 and Sato,  Y. and Kajihara, Seiji and 梶原, 誠司 and Girard,  P. and Tehranipoor,  M. and Wang,  L.-T.},
 journal = {2013 22nd Asian Test Symposium},
 month = {Dec},
 note = {The applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses for good chips. Different from conventional low-power BIST, this paper is the first that has explicitly focused on achieving capture power safety with a practical scheme called capture-power-safe BIST (CPS-BIST). The basic idea is to identify all possibly erroneous test responses and use the well-known technique of mask (partial-mask or full-mask) to block them from reaching the MISR. Experiments with large benchmark and industrial circuits show that CPS-BIST can achieve capture power safety with negligible impact on both test quality and area overhead., 2013 22nd Asian Test Symposium, 18-21 November 2013, Jiaosi Township, Taiwan},
 pages = {19--24},
 title = {On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST},
 year = {2013},
 yomi = {オン, ギョウセイ and カジハラ, セイジ}
}