@article{oai:kyutech.repo.nii.ac.jp:00006389,
 author = {Wen, Xiaoqing and 温, 暁青 and Yamashita,  Yoshiyuki and Morishima,  Shohei and Kajihara, Seiji and 梶原, 誠司 and Wang,  Laung-Terng and Saluja,  Kewal K. and Kinoshita,  Kozo},
 journal = {IEEE International Conference on Test, 2005},
 month = {Feb},
 note = {Scan-based at-speed testing is a key technology to guarantee timing-related test quality in the deep submicron era. However, its applicability is being severely challenged since significant yield loss may occur from circuit malfunction due to excessive IR drop caused by high power dissipation when a test response is captured. This paper addresses this critical problem with a novel low-capture-power X-filling method of assigning 0's and 1's to unspecified (X) bits in a test cube obtained during ATPG. This method reduces the circuit switching activity in capture mode and can be easily incorporated into any test generation flow to achieve capture power reduction without any area, timing, or fault coverage impact. Test vectors generated with this practical method greatly improve the applicability of scan-based at-speed testing by reducing the risk of test yield loss, IEEE International Conference on Test, 2005, 8 November 2005, Austin, TX, USA},
 title = {Low-capture-power test generation for scan-based at-speed testing},
 year = {2006},
 yomi = {オン, ギョウセイ and カジハラ, セイジ}
}