@article{oai:kyutech.repo.nii.ac.jp:00006394,
 author = {Wang,  Laung-Terng and Wen, Xiaoqing and 温, 暁青 and Furukawa,  Hiroshi and Hsu,  Fei-Sheng and Lin,  Shyh-Horng and Tsai,  Sen-Wei and Abdel-Hafez,  Khader S. and Wu,  Shianling},
 journal = {2004 International Conference on Test},
 month = {Jan},
 note = {This work describes the VirtualScan technology for scan test cost reduction. Scan chains in a VirtualScan circuit are split into shorter ones and the gap between external scan ports and internal scan chains are bridged with a broadcaster and a compactor. Test patterns for a VirtualScan circuit are generated directly by one-pass VirtualScan ATPG, in which multi-capture clocking and maximum test compaction are supported. In addition, VirtualScan ATPG avoids unknown-value and aliasing effects algorithmically without adding any additional circuitry. The VirtualScan technology has achieved successful tape-outs of industrial chips and has been proven to be an efficient and easy-to-implement solution for scan test cost reduction., 2004 International Conference on Test, 26-28 October 2004, Charlotte, NC, USA, USA},
 title = {VirtualScan: a new compressed scan technology for test cost reduction},
 year = {2005},
 yomi = {オン, ギョウセイ}
}