@article{oai:kyutech.repo.nii.ac.jp:00006395,
 author = {Cheon,  B. and Lee,  E. and Wang,  L.-T. and Wen, Xiaoqing and 温, 暁青 and Hsu,  P. and Cho,  J. and Park,  J. and Chao,  H. and Wu,  S.},
 journal = {Design, Automation and Test in Europe},
 month = {Mar},
 note = {This paper describes a flexible logic BIST scheme that features high fault coverage achieved by fault-simulation guided test point insertion, real at-speed test capability for multi-clock designs without clock frequency manipulation, and easy physical implementation due to the use of a low-speed SE signal. Application results of this scheme to two widely used IP cores are also reported., Design, Automation and Test in Europe (DATE05), 7-11 March 2005, Munich, Germany},
 title = {At-Speed Logic BIST for IP Cores},
 year = {2005},
 yomi = {オン, ギョウセイ}
}