@article{oai:kyutech.repo.nii.ac.jp:00006398,
 author = {Lin,  Yi-Tsung and Huang,  Jiun-Lang and Wen, Xiaoqing and 温, 暁青},
 journal = {2011 IEEE International Test Conference},
 month = {Jan},
 note = {Capture power management has become a necessity to avoid at-speed scan testing yield loss, especially for modern complex and low power designs. This paper proposes a test pattern generation methodology that utilizes the available clock-gating mechanism, a popular low power design technique, to reduce the launch cycle weighted switching activity (WSA) for at-speed scan testing. Compared to previous techniques that consider clock-gating, a significant launch cycle WSA reduction is achieved without severe test pattern inflation., 2011 IEEE International Test Conference, 20-22 September 2011, Anaheim, CA, USA},
 title = {Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing},
 year = {2012},
 yomi = {オン, ギョウセイ}
}