{"created":"2023-05-15T11:59:48.095765+00:00","id":6398,"links":{},"metadata":{"_buckets":{"deposit":"fdb1413c-0dfb-43be-a63c-0f0cb854305b"},"_deposit":{"created_by":3,"id":"6398","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"6398"},"status":"published"},"_oai":{"id":"oai:kyutech.repo.nii.ac.jp:00006398","sets":["8:24"]},"author_link":["26786","26787","26783","26784","1143"],"item_21_alternative_title_18":{"attribute_name":"その他のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Testing"}]},"item_21_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2012-01-26","bibliographicIssueDateType":"Issued"},"bibliographic_titles":[{"bibliographic_title":"2011 IEEE International Test Conference"}]}]},"item_21_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Capture power management has become a necessity to avoid at-speed scan testing yield loss, especially for modern complex and low power designs. This paper proposes a test pattern generation methodology that utilizes the available clock-gating mechanism, a popular low power design technique, to reduce the launch cycle weighted switching activity (WSA) for at-speed scan testing. Compared to previous techniques that consider clock-gating, a significant launch cycle WSA reduction is achieved without severe test pattern inflation.","subitem_description_type":"Abstract"}]},"item_21_description_5":{"attribute_name":"内容記述","attribute_value_mlt":[{"subitem_description":"2011 IEEE International Test Conference, 20-22 September 2011, Anaheim, CA, USA","subitem_description_type":"Other"}]},"item_21_description_60":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"subitem_description":"Journal Article","subitem_description_type":"Other"}]},"item_21_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"nameIdentifiers":[{"nameIdentifier":"26786","nameIdentifierScheme":"WEKO"}],"names":[{"name":"Lin,  Y.-T."}]},{"nameIdentifiers":[{"nameIdentifier":"26787","nameIdentifierScheme":"WEKO"}],"names":[{"name":"Huang,  J.-L."}]},{"affiliations":[{"affiliationNames":[{"affiliationName":"","lang":"ja"}],"nameIdentifiers":[]}],"familyNames":[{"familyName":"Wen","familyNameLang":"en"},{"familyName":"温","familyNameLang":"ja"},{"familyName":"オン","familyNameLang":"ja-Kana"}],"givenNames":[{"givenName":"Xiaoqing","givenNameLang":"en"},{"givenName":"暁青","givenNameLang":"ja"},{"givenName":"ギョウセイ","givenNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"1143","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"20250897","nameIdentifierScheme":"e-Rad","nameIdentifierURI":"https://nrid.nii.ac.jp/ja/nrid/1000020250897"},{"nameIdentifier":"7201738030","nameIdentifierScheme":"Scopus著者ID","nameIdentifierURI":"https://www.scopus.com/authid/detail.uri?authorId=7201738030"},{"nameIdentifier":"300","nameIdentifierScheme":"九工大研究者情報","nameIdentifierURI":"https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html"}],"names":[{"name":"Wen, Xiaoqing","nameLang":"en"},{"name":"温, 暁青","nameLang":"ja"},{"name":"オン, ギョウセイ","nameLang":"ja-Kana"}]}]},"item_21_link_62":{"attribute_name":"研究者情報","attribute_value_mlt":[{"subitem_link_url":"https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html"}]},"item_21_publisher_7":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEEE"}]},"item_21_relation_12":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"info:doi/10.1109/TEST.2011.6139132","subitem_relation_type_select":"DOI"}}]},"item_21_relation_14":{"attribute_name":"情報源","attribute_value_mlt":[{"subitem_relation_name":[{"subitem_relation_name_text":"DOI: 10.1109/TEST.2011.6139132"}],"subitem_relation_type_id":{"subitem_relation_type_id_text":"DOI: 10.1109/TEST.2011.6139132","subitem_relation_type_select":"URI"}}]},"item_21_relation_9":{"attribute_name":"ISBN","attribute_value_mlt":[{"subitem_relation_type_id":{"subitem_relation_type_id_text":"978-1-4577-0153-5","subitem_relation_type_select":"ISBN"}},{"subitem_relation_type_id":{"subitem_relation_type_id_text":"978-1-4577-0152-8","subitem_relation_type_select":"ISBN"}},{"subitem_relation_type_id":{"subitem_relation_type_id_text":"978-1-4577-0151-1","subitem_relation_type_select":"ISBN"}}]},"item_21_rights_13":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"Copyright (c) 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works."}]},"item_21_select_59":{"attribute_name":"査読の有無","attribute_value_mlt":[{"subitem_select_item":"yes"}]},"item_21_source_id_8":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2378-2250","subitem_source_identifier_type":"ISSN"},{"subitem_source_identifier":"1089-3539","subitem_source_identifier_type":"ISSN"},{"subitem_source_identifier":"1089-3539","subitem_source_identifier_type":"ISSN"}]},"item_21_subject_16":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"548","subitem_subject_scheme":"NDC"}]},"item_21_text_28":{"attribute_name":"論文ID（連携）","attribute_value_mlt":[{"subitem_text_value":"10232916"}]},"item_21_text_36":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan"},{"subitem_text_value":"Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan"},{"subitem_text_value":"Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka 820-8502, Japan"}]},"item_21_text_63":{"attribute_name":"連携ID","attribute_value_mlt":[{"subitem_text_value":"8117"}]},"item_21_version_type_58":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_ab4af688f83e57aa","subitem_version_type":"AM"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Lin,  Yi-Tsung"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Huang,  Jiun-Lang"}],"nameIdentifiers":[{}]},{"creatorAffiliations":[{"affiliationNameIdentifiers":[],"affiliationNames":[{"affiliationName":""}]}],"creatorNames":[{"creatorName":"Wen, Xiaoqing","creatorNameLang":"en"},{"creatorName":"温, 暁青","creatorNameLang":"ja"},{"creatorName":"オン, ギョウセイ","creatorNameLang":"ja-Kana"}],"familyNames":[{},{},{}],"givenNames":[{},{},{}],"nameIdentifiers":[{},{},{},{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-02-10"}],"displaytype":"detail","filename":"10232916.pdf","filesize":[{"value":"154.7 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"10232916.pdf","url":"https://kyutech.repo.nii.ac.jp/record/6398/files/10232916.pdf"},"version_id":"ebdb4a30-4d2c-43cd-90ae-ab981af98ccb"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"test pattern generation","subitem_subject_scheme":"Other"},{"subitem_subject":"clock-gating","subitem_subject_scheme":"Other"},{"subitem_subject":"test power reduction","subitem_subject_scheme":"Other"},{"subitem_subject":"at-speed testing","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing"}]},"item_type_id":"21","owner":"3","path":["24"],"pubdate":{"attribute_name":"公開日","attribute_value":"2020-02-10"},"publish_date":"2020-02-10","publish_status":"0","recid":"6398","relation_version_is_last":true,"title":["Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2023-10-25T08:51:35.310014+00:00"}