{"created":"2023-05-15T11:59:48.759590+00:00","id":6414,"links":{},"metadata":{"_buckets":{"deposit":"7a66fe5f-2529-498c-ab09-cff1051d0b70"},"_deposit":{"created_by":3,"id":"6414","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"6414"},"status":"published"},"_oai":{"id":"oai:kyutech.repo.nii.ac.jp:00006414","sets":["8:24"]},"author_link":["1143"],"item_21_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2017-08-03","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"588","bibliographicPageStart":"585","bibliographic_titles":[{"bibliographic_title":"2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)"}]}]},"item_21_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Low-power VLSI circuits are indispensable for almost all types of modern electronic devices, from battery-driven mobile gadgets to harvested-energy-driven wireless sensor systems. However, the testing of such low-power VLSI circuits has become a big challenge, especially due to the excessive power dissipation during scan testing. This paper will highlight three major test-power-induced problems (namely heat, false failures, clock stretch) and describe how to mitigate them with power-aware VLSI testing. Future research topics in this field will also be discussed.","subitem_description_type":"Abstract"}]},"item_21_description_5":{"attribute_name":"内容記述","attribute_value_mlt":[{"subitem_description":"13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT-2016), 25-28 October 2016, Hangzhou, China","subitem_description_type":"Other"}]},"item_21_description_60":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"subitem_description":"Journal Article","subitem_description_type":"Other"}]},"item_21_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"affiliations":[{"affiliationNames":[{"affiliationName":"","lang":"ja"}],"nameIdentifiers":[]}],"familyNames":[{"familyName":"Wen","familyNameLang":"en"},{"familyName":"温","familyNameLang":"ja"},{"familyName":"オン","familyNameLang":"ja-Kana"}],"givenNames":[{"givenName":"Xiaoqing","givenNameLang":"en"},{"givenName":"暁青","givenNameLang":"ja"},{"givenName":"ギョウセイ","givenNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"1143","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"20250897","nameIdentifierScheme":"e-Rad","nameIdentifierURI":"https://nrid.nii.ac.jp/ja/nrid/1000020250897"},{"nameIdentifier":"7201738030","nameIdentifierScheme":"Scopus著者ID","nameIdentifierURI":"https://www.scopus.com/authid/detail.uri?authorId=7201738030"},{"nameIdentifier":"300","nameIdentifierScheme":"九工大研究者情報","nameIdentifierURI":"https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html"}],"names":[{"name":"Wen, Xiaoqing","nameLang":"en"},{"name":"温, 暁青","nameLang":"ja"},{"name":"オン, ギョウセイ","nameLang":"ja-Kana"}]}]},"item_21_link_62":{"attribute_name":"研究者情報","attribute_value_mlt":[{"subitem_link_url":"https://hyokadb02.jimu.kyutech.ac.jp/html/300_ja.html"}]},"item_21_publisher_7":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEEE"}]},"item_21_relation_12":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"https://doi.org/10.1109/ICSICT.2016.7998986","subitem_relation_type_select":"DOI"}}]},"item_21_relation_9":{"attribute_name":"ISBN","attribute_value_mlt":[{"subitem_relation_type_id":{"subitem_relation_type_id_text":"978-1-4673-9717-9","subitem_relation_type_select":"ISBN"}},{"subitem_relation_type_id":{"subitem_relation_type_id_text":"978-1-4673-9719-3","subitem_relation_type_select":"ISBN"}},{"subitem_relation_type_id":{"subitem_relation_type_id_text":"978-1-4673-9718-6","subitem_relation_type_select":"ISBN"}},{"subitem_relation_type_id":{"subitem_relation_type_id_text":"978-1-4673-9720-9","subitem_relation_type_select":"ISBN"}}]},"item_21_rights_13":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"Copyright (c) 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works."}]},"item_21_select_59":{"attribute_name":"査読の有無","attribute_value_mlt":[{"subitem_select_item":"yes"}]},"item_21_subject_16":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"548","subitem_subject_scheme":"NDC"}]},"item_21_text_28":{"attribute_name":"論文ID（連携）","attribute_value_mlt":[{"subitem_text_value":"10317319"}]},"item_21_text_36":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Department of Computer Systems and Electronics, Kyushu Institute of Technology, Kawazu 680-4, Iizuka, 820-8502, Japan"}]},"item_21_text_63":{"attribute_name":"連携ID","attribute_value_mlt":[{"subitem_text_value":"8130"}]},"item_21_version_type_58":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_ab4af688f83e57aa","subitem_version_type":"AM"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorAffiliations":[{"affiliationNameIdentifiers":[],"affiliationNames":[{"affiliationName":""}]}],"creatorNames":[{"creatorName":"Wen, Xiaoqing","creatorNameLang":"en"},{"creatorName":"温, 暁青","creatorNameLang":"ja"},{"creatorName":"オン, ギョウセイ","creatorNameLang":"ja-Kana"}],"familyNames":[{},{},{}],"givenNames":[{},{},{}],"nameIdentifiers":[{},{},{},{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-02-19"}],"displaytype":"detail","filename":"10317319.pdf","filesize":[{"value":"833.3 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"10317319.pdf","url":"https://kyutech.repo.nii.ac.jp/record/6414/files/10317319.pdf"},"version_id":"e9f58462-a0a8-4231-a544-5636f884cd96"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Clocks","subitem_subject_scheme":"Other"},{"subitem_subject":"Switches","subitem_subject_scheme":"Other"},{"subitem_subject":"Testing","subitem_subject_scheme":"Other"},{"subitem_subject":"Very large scale integration","subitem_subject_scheme":"Other"},{"subitem_subject":"Logic gates","subitem_subject_scheme":"Other"},{"subitem_subject":"Lead","subitem_subject_scheme":"Other"},{"subitem_subject":"Flip-flops","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Power-Aware Testing For Low-Power VLSI Circuits","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Power-Aware Testing For Low-Power VLSI Circuits"}]},"item_type_id":"21","owner":"3","path":["24"],"pubdate":{"attribute_name":"公開日","attribute_value":"2020-02-19"},"publish_date":"2020-02-19","publish_status":"0","recid":"6414","relation_version_is_last":true,"title":["Power-Aware Testing For Low-Power VLSI Circuits"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2023-10-25T08:51:32.078028+00:00"}