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アイテム
パルス結合位相振動子のマルチFPGA実装とその応用
https://doi.org/10.18997/00007804
https://doi.org/10.18997/0000780431a1aeef-0749-4f8f-9948-059b9ceb24ab
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
sei_k_371.pdf (8.3 MB)
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| アイテムタイプ | 学位論文 = Thesis or Dissertation(1) | |||||||
|---|---|---|---|---|---|---|---|---|
| 公開日 | 2020-06-16 | |||||||
| 資源タイプ | ||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_db06 | |||||||
| 資源タイプ | doctoral thesis | |||||||
| タイトル | ||||||||
| タイトル | Multi-FPGA Implementation of Pulse-coupled Phase Oscillators and its Applications | |||||||
| 言語 | en | |||||||
| タイトル | ||||||||
| タイトル | パルス結合位相振動子のマルチFPGA実装とその応用 | |||||||
| 言語 | ja | |||||||
| 言語 | ||||||||
| 言語 | eng | |||||||
| 著者 |
Pramanta, Dinda
× Pramanta, Dinda
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| 抄録 | ||||||||
| 内容記述タイプ | Abstract | |||||||
| 内容記述 | Recent advances in neurosciences, Spiking Neural Networks （SNNs） overcome the computational power of neural networks made into strong ability to fast adaptation for neurocomputing. A typical SNNs has been used as an internal layer of reservoir computing （RC）. RC is a framework for constructing the recurrent neural networks, which is used for modeling the parts of the brain to solve the temporal problem. However, the networks computation requires a high computational complexity, which affected to simulation-time and resources. Hardware approach provides a very realistic real-time implementation. Field Programmable Gate Array （FPGA） is a semiconductor device that based on configurable logic blocks （CLBs） circuit has the reconfigure ability. Using the Winfree's model of pulse-coupled phase oscillators （PCPO） as a spike generator, single board processing of FPGA has the limitation resources and cost, also maintaining the synchronizing part between each oscillator requires a high-speed transmission. In order to verify the PCPO for RC based, checking the fundamental system PCPO for RC including the critical dynamics phenomenon is necessary. The purpose in this study is to implement the PCPOs using multi-FPGA for achieving the acceleration speed computation for fast-synchronizations and investigate the feasibility of PCPO for RC. The results of PCPOs using multi-FPGA were implemented and carried out on a hardware level onto FPGA synthesizer of Xilinx Tools. From the block proposed system, Virtex6-Ml605s were used to implement 10 x 10 oscillators over two FPGAs and the stability edge phenomenon proves that the 10 x 10 of PCPO with neighbor topology connections within one FPGA, lead to the random-like spiking. The proposed model works properly in the time series generation task. PCPO for RC succeed to be implemented on hardware level using ML605-Virtex6 with low amount of resources. | |||||||
| 目次 | ||||||||
| 内容記述タイプ | TableOfContents | |||||||
| 内容記述 | 1 Introduction||2 Literature review on Neurocomputing||3 Multi-Field Programmable Gate Arrays||4 FPGA's Application for Reservoir Computing||5 Analysis and Discussion||6 Conclusions and Future works | |||||||
| 備考 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | 九州工業大学博士学位論文 学位記番号：生工博甲第371号 学位授与年月日：令和2年3月25日 | |||||||
| キーワード | ||||||||
| 主題Scheme | Other | |||||||
| 主題 | PCPO | |||||||
| キーワード | ||||||||
| 主題Scheme | Other | |||||||
| 主題 | FPGA | |||||||
| キーワード | ||||||||
| 主題Scheme | Other | |||||||
| 主題 | Synchronizations | |||||||
| キーワード | ||||||||
| 主題Scheme | Other | |||||||
| 主題 | Multi-FPGA | |||||||
| キーワード | ||||||||
| 主題Scheme | Other | |||||||
| 主題 | Neurocomputing | |||||||
| キーワード | ||||||||
| 主題Scheme | Other | |||||||
| 主題 | Reservoir Computing | |||||||
| アドバイザー | ||||||||
| 田向, 権 | ||||||||
| 学位授与番号 | ||||||||
| 学位授与番号 | 甲第371号 | |||||||
| 学位名 | ||||||||
| 学位名 | 博士（工学） | |||||||
| 学位授与年月日 | ||||||||
| 学位授与年月日 | 2020-03-25 | |||||||
| 学位授与機関 | ||||||||
| 学位授与機関識別子Scheme | kakenhi | |||||||
| 学位授与機関識別子 | 17104 | |||||||
| 学位授与機関名 | 九州工業大学 | |||||||
| 学位授与年度 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | 令和元年度 | |||||||
| 出版タイプ | ||||||||
| 出版タイプ | VoR | |||||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||
| アクセス権 | ||||||||
| アクセス権 | open access | |||||||
| アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||||
| ID登録 | ||||||||
| ID登録 | 10.18997/00007804 | |||||||
| ID登録タイプ | JaLC | |||||||
