@article{oai:kyutech.repo.nii.ac.jp:00006948,
 author = {Miyake,  Yousuke and Sato,  Yasuo and Kajihara, Seiji and 梶原, 誠司},
 journal = {2019 IEEE 24th Pacific Rim International Symposium on Dependable Computing (PRDC)},
 month = {Jan},
 note = {Avoidance of delay-related failures due to aging phenomena is an important issue of current VLSI systems. Delay measurement in field is effective for detection of aging-induced delay increase. This paper proposes a delay measurement method using BIST (Built-In Self-Test) in an FPGA. The proposed method consists of variable test timing generation using an embedded PLL, BIST-based delay measurement, and correction of the measured delay with reflecting temperature variance in field. In on-chip delay measurement of the proposed method, the fastest operating speed is checked by repeating delay test with several test timings. Because circuit delay is influenced by temperature during measurement, the measured delay is then corrected according to the temperature during testing. Based on test log including the corrected delay, delay degradation and aging detection can be grasped. In evaluation experiments of the propose method implemented on an Intel Cyclone IV FPGA device (60nm technology), variable test timing generation realized 96 ps timing step resolution (that is below 1% of the system clock), correction process for measured delay could reduce influence of temperature variation. Furthermore, its feasibility of the proposed method for aging detection is discussed in this paper., 24th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2019), December 1-3, 2019, Kyoto, Japan},
 pages = {130--137},
 title = {On-Chip Delay Measurement for In-Field Test of FPGAs},
 year = {2020},
 yomi = {カジハラ, セイジ}
}