{"created":"2023-05-15T12:00:13.487097+00:00","id":6948,"links":{},"metadata":{"_buckets":{"deposit":"8b5fb29f-94c6-4ead-94d2-541ced9fcb7f"},"_deposit":{"created_by":3,"id":"6948","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"6948"},"status":"published"},"_oai":{"id":"oai:kyutech.repo.nii.ac.jp:00006948","sets":["8:24"]},"author_link":["1147","29866","29869","29865","29868"],"item_21_alternative_title_18":{"attribute_name":"その他のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"On-chip delay measurement for in-field test of FPGAs"}]},"item_21_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2020-01-09","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"137","bibliographicPageStart":"130","bibliographic_titles":[{"bibliographic_title":"2019 IEEE 24th Pacific Rim International Symposium on Dependable Computing (PRDC)"}]}]},"item_21_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Avoidance of delay-related failures due to aging phenomena is an important issue of current VLSI systems. Delay measurement in field is effective for detection of aging-induced delay increase. This paper proposes a delay measurement method using BIST (Built-In Self-Test) in an FPGA. The proposed method consists of variable test timing generation using an embedded PLL, BIST-based delay measurement, and correction of the measured delay with reflecting temperature variance in field. In on-chip delay measurement of the proposed method, the fastest operating speed is checked by repeating delay test with several test timings. Because circuit delay is influenced by temperature during measurement, the measured delay is then corrected according to the temperature during testing. Based on test log including the corrected delay, delay degradation and aging detection can be grasped. In evaluation experiments of the propose method implemented on an Intel Cyclone IV FPGA device (60nm technology), variable test timing generation realized 96 ps timing step resolution (that is below 1% of the system clock), correction process for measured delay could reduce influence of temperature variation. Furthermore, its feasibility of the proposed method for aging detection is discussed in this paper.","subitem_description_type":"Abstract"}]},"item_21_description_5":{"attribute_name":"内容記述","attribute_value_mlt":[{"subitem_description":"24th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2019), December 1-3, 2019, Kyoto, Japan","subitem_description_type":"Other"}]},"item_21_description_60":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"subitem_description":"Journal Article","subitem_description_type":"Other"}]},"item_21_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"nameIdentifiers":[{"nameIdentifier":"29868","nameIdentifierScheme":"WEKO"}],"names":[{"name":"Miyake,  Y."}]},{"nameIdentifiers":[{"nameIdentifier":"29869","nameIdentifierScheme":"WEKO"}],"names":[{"name":"Sato,  Y."}]},{"affiliations":[{"affiliationNames":[{"affiliationName":"","lang":"ja"}],"nameIdentifiers":[]}],"familyNames":[{"familyName":"Kajihara","familyNameLang":"en"},{"familyName":"梶原","familyNameLang":"ja"},{"familyName":"カジハラ","familyNameLang":"ja-Kana"}],"givenNames":[{"givenName":"Seiji","givenNameLang":"en"},{"givenName":"誠司","givenNameLang":"ja"},{"givenName":"セイジ","givenNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"1147","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"80252592","nameIdentifierScheme":"e-Rad","nameIdentifierURI":"https://nrid.nii.ac.jp/ja/nrid/1000080252592"},{"nameIdentifier":"7005061314","nameIdentifierScheme":"Scopus著者ID","nameIdentifierURI":"https://www.scopus.com/authid/detail.uri?authorId=7005061314"},{"nameIdentifier":"201","nameIdentifierScheme":"九工大研究者情報","nameIdentifierURI":"https://hyokadb02.jimu.kyutech.ac.jp/html/201_ja.html"}],"names":[{"name":"Kajihara, Seiji","nameLang":"en"},{"name":"梶原, 誠司","nameLang":"ja"},{"name":"カジハラ, セイジ","nameLang":"ja-Kana"}]}]},"item_21_link_62":{"attribute_name":"研究者情報","attribute_value_mlt":[{"subitem_link_url":"https://hyokadb02.jimu.kyutech.ac.jp/html/201_ja.html"}]},"item_21_publisher_7":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEEE"}]},"item_21_relation_12":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"https://doi.org/10.1109/PRDC47002.2019.00043","subitem_relation_type_select":"DOI"}}]},"item_21_relation_9":{"attribute_name":"ISBN","attribute_value_mlt":[{"subitem_relation_type_id":{"subitem_relation_type_id_text":"978-1-7281-4961-5","subitem_relation_type_select":"ISBN"}},{"subitem_relation_type_id":{"subitem_relation_type_id_text":"978-1-7281-4962-2","subitem_relation_type_select":"ISBN"}}]},"item_21_rights_13":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"Copyright (c) 2020 IEEE. Personal use of this material is permitted.  Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works."}]},"item_21_select_59":{"attribute_name":"査読の有無","attribute_value_mlt":[{"subitem_select_item":"yes"}]},"item_21_source_id_8":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2473-3105","subitem_source_identifier_type":"ISSN"},{"subitem_source_identifier":"1555-094X","subitem_source_identifier_type":"ISSN"}]},"item_21_subject_16":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"548","subitem_subject_scheme":"NDC"}]},"item_21_text_28":{"attribute_name":"論文ID（連携）","attribute_value_mlt":[{"subitem_text_value":"10362956"}]},"item_21_text_36":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Kyushu Institute of Technology"},{"subitem_text_value":"Kyushu Institute of Technology"},{"subitem_text_value":"Kyushu Institute of Technology"}]},"item_21_text_63":{"attribute_name":"連携ID","attribute_value_mlt":[{"subitem_text_value":"8662"}]},"item_21_version_type_58":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_ab4af688f83e57aa","subitem_version_type":"AM"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Miyake,  Yousuke"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Sato,  Yasuo"}],"nameIdentifiers":[{}]},{"creatorAffiliations":[{"affiliationNameIdentifiers":[],"affiliationNames":[{"affiliationName":""}]}],"creatorNames":[{"creatorName":"Kajihara, Seiji","creatorNameLang":"en"},{"creatorName":"梶原, 誠司","creatorNameLang":"ja"},{"creatorName":"カジハラ, セイジ","creatorNameLang":"ja-Kana"}],"familyNames":[{},{},{}],"givenNames":[{},{},{}],"nameIdentifiers":[{},{},{},{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2021-04-07"}],"displaytype":"detail","filename":"10362956.pdf","filesize":[{"value":"639.7 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"10362956.pdf","url":"https://kyutech.repo.nii.ac.jp/record/6948/files/10362956.pdf"},"version_id":"debdd134-0991-48e2-873d-4087bc3e5a20"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"FPGA","subitem_subject_scheme":"Other"},{"subitem_subject":"Field test","subitem_subject_scheme":"Other"},{"subitem_subject":"Periodic Test","subitem_subject_scheme":"Other"},{"subitem_subject":"Delay measurement","subitem_subject_scheme":"Other"},{"subitem_subject":"Deterioration detection","subitem_subject_scheme":"Other"},{"subitem_subject":"Temperature sensor","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"On-Chip Delay Measurement for In-Field Test of FPGAs","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"On-Chip Delay Measurement for In-Field Test of FPGAs"}]},"item_type_id":"21","owner":"3","path":["24"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-04-07"},"publish_date":"2021-04-07","publish_status":"0","recid":"6948","relation_version_is_last":true,"title":["On-Chip Delay Measurement for In-Field Test of FPGAs"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2023-10-25T08:51:57.165987+00:00"}