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A shared synapse architecture for efficient FPGA implementation of autoencoders
http://hdl.handle.net/10228/00008262
http://hdl.handle.net/10228/00008262f8257f53-14d0-4ca1-8bca-0087a1eec765
| 名前 / ファイル | ライセンス | アクション |
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journal.pone.0194049.pdf (12.4 MB)
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| Item type | 学術雑誌論文 = Journal Article(1) | |||||||||||||||||||||
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| 公開日 | 2021-05-20 | |||||||||||||||||||||
| 資源タイプ | ||||||||||||||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||||||||||||||
| 資源タイプ | journal article | |||||||||||||||||||||
| タイトル | ||||||||||||||||||||||
| タイトル | A shared synapse architecture for efficient FPGA implementation of autoencoders | |||||||||||||||||||||
| 言語 | en | |||||||||||||||||||||
| 言語 | ||||||||||||||||||||||
| 言語 | eng | |||||||||||||||||||||
| 著者 |
Suzuki, Akihiro
× Suzuki, Akihiro× 森江, 隆
WEKO
1615
× 田向, 権
WEKO
6059
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| 抄録 | ||||||||||||||||||||||
| 内容記述タイプ | Abstract | |||||||||||||||||||||
| 内容記述 | This paper proposes a shared synapse architecture for autoencoders (AEs), and implements an AE with the proposed architecture as a digital circuit on a field-programmable gate array (FPGA). In the proposed architecture, the values of the synapse weights are shared between the synapses of an input and a hidden layer, and between the synapses of a hidden and an output layer. This architecture utilizes less of the limited resources of an FPGA than an architecture which does not share the synapse weights, and reduces the amount of synapse modules used by half. For the proposed circuit to be implemented into various types of AEs, it utilizes three kinds of parameters; one to change the number of layers’ units, one to change the bit width of an internal value, and a learning rate. By altering a network configuration using these parameters, the proposed architecture can be used to construct a stacked AE. The proposed circuits are logically synthesized, and the number of their resources is determined. Our experimental results show that single and stacked AE circuits utilizing the proposed shared synapse architecture operate as regular AEs and as regular stacked AEs. The scalability of the proposed circuit and the relationship between the bit widths and the learning results are also determined. The clock cycles of the proposed circuits are formulated, and this formula is used to estimate the theoretical performance of the circuit when the circuit is used to construct arbitrary networks. | |||||||||||||||||||||
| 言語 | en | |||||||||||||||||||||
| 書誌情報 |
en : PLoS ONE 巻 13, 号 3, p. e0194049, 発行日 2018-03-15 |
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| 出版社 | ||||||||||||||||||||||
| 出版者 | Public Library of Science | |||||||||||||||||||||
| 言語 | en | |||||||||||||||||||||
| DOI | ||||||||||||||||||||||
| 関連タイプ | isIdenticalTo | |||||||||||||||||||||
| 識別子タイプ | DOI | |||||||||||||||||||||
| 関連識別子 | https://doi.org/10.1371/journal.pone.0194049 | |||||||||||||||||||||
| 日本十進分類法 | ||||||||||||||||||||||
| 主題Scheme | NDC | |||||||||||||||||||||
| 主題 | 548 | |||||||||||||||||||||
| ISSN | ||||||||||||||||||||||
| 収録物識別子タイプ | EISSN | |||||||||||||||||||||
| 収録物識別子 | 1932-6203 | |||||||||||||||||||||
| 著作権関連情報 | ||||||||||||||||||||||
| 権利情報 | Copyright (c) 2018 Suzuki et al. | |||||||||||||||||||||
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| 権利情報Resource | http://creativecommons.org/licenses/by/4.0/ | |||||||||||||||||||||
| 権利情報 | This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited. | |||||||||||||||||||||
| 出版タイプ | ||||||||||||||||||||||
| 出版タイプ | VoR | |||||||||||||||||||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||||||||||||||||
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| 値 | yes | |||||||||||||||||||||
| 研究者情報 | ||||||||||||||||||||||
| URL | https://hyokadb02.jimu.kyutech.ac.jp/html/100000641_ja.html | |||||||||||||||||||||
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| 値 | 10327847 | |||||||||||||||||||||
| 連携ID | ||||||||||||||||||||||
| 値 | 8845 | |||||||||||||||||||||
