The Study and Development of Hardware Oriented Dropout Algorithm for Efficient FPGA Implementation

Yeoh,  Yoeng Jye

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FPGA実装のため効率的なハードウェア指向ドロップアウトアルゴリズムの研究開発

https://doi.org/10.18997/00008355

名前 / ファイル	ライセンス	アクション
sei_k_400.pdf (6.2 MB)

アイテムタイプ

学位論文 = Thesis or Dissertation(1)

公開日

2021-06-09

資源タイプ

資源タイプ識別子

http://purl.org/coar/resource_type/c_db06

資源タイプ

doctoral thesis

タイトル

The Study and Development of Hardware Oriented Dropout Algorithm for Efficient FPGA Implementation

言語

タイトル

FPGA実装のため効率的なハードウェア指向ドロップアウトアルゴリズムの研究開発

言語

eng

著者

Yeoh, Yoeng Jye

抄録

内容記述タイプ

Abstract

内容記述

The research and developments of Deep Neural Networks （DNNs） have been caught attention as DNNs have demonstrated promising performance in numerous fields such as robotics, medical, automotive, manufacturing and others. The recent DNNs are going deeper, larger and more complex to adapt to different tasks with higher accuracy. Training neural networks is time-, resource- and power-intensive as the number of parameters increase. Various study and research have been published in applying DNNs into embedded systems and portable devices such as service robots, mobile phones, autonomous vehicle and so on. These widen the application of DNNs. However, the computation speed and power consumption are the concern due to the complex computation. Training DNNs in embedded systems is difficult to achieve without compromising among the accuracy, speed and power. Field programmable gate arrays （FPGAs） are suitable device for embedded systems due to their parallel processing and low power consumption characteristics. However, general algorithms for software implementation are not suitable for FPGA owing to differences in their architectures, causing reduce in speed and increase the resources required. Therefore, modified algorithms are required for efficient implementation into FPGA. In this thesis, the hardware oriented dropout algorithm has been proposed for efficient FPGA implementation. Dropout algorithm is a regularization technique that commonly used in DNNs to overcome the overfitting problem, the problem that the DNNs are over-trained and well adapted to training data, resulting performance drop when it comes to unseen data. By randomly dropping the neurons during training phase, dropout technique omits the feature detectors and prevents complex co-adaptions between neurons. In general dropout method, random numbers where generated from random number generators （RNGs） are used to compare with dropout ratio to determine the activation or deactivation of neurons. However, RNGs and comparators are resources consuming in FPGA and implementation of RNGs in FPGA are deep and huge topics. Instead, the proposed algorithm attempts to eliminate the required of RNGs and comparators, reduce the complexity and achieve the equal effect of dropout with least resources and high speed. The proposed method was verified through two approaches: software verification and hardware verification. In software verification, the performance of proposed dropout was analyzed with multiple pairs of neural networks and datasets to ensure the robustness. Whereas in hardware verification, the resource consumption and speed of proposed dropout were compared to the general dropout in showing the effectiveness of FPGA implementation.

内容記述タイプ

TableOfContents

内容記述

1 Introduction||2 Literature Review||3 Methodology||4 Simulation and Implementation||5 Experiment Results and Discussion||6 Conclusion and Future Works

備考

内容記述タイプ

Other

内容記述

九州工業大学博士学位論文学位記番号：生工博甲第400号学位授与年月日：令和3年3月25日

キーワード

主題Scheme

Other

主題

Deep Neural Networks

キーワード

主題Scheme

Other

主題

Dropout

キーワード

主題Scheme

Other

主題

FPGA

キーワード

主題Scheme

Other

主題

Hardware

キーワード

主題Scheme

Other

主題

Human Intelligence

アドバイザー

田向, 権

学位授与番号

甲第400号

学位名

博士（工学）

学位授与年月日

2021-03-25

学位授与機関

学位授与機関識別子Scheme

kakenhi

学位授与機関識別子

17104

学位授与機関名

九州工業大学

学位授与年度

内容記述タイプ

Other

内容記述

令和2年度

出版タイプ

VoR

出版タイプResource

http://purl.org/coar/version/c_970fb48d4fbd8a85

アクセス権

open access

アクセス権URI

http://purl.org/coar/access_right/c_abf2

ID登録

10.18997/00008355

ID登録タイプ

JaLC

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FPGA実装のため効率的なハードウェア指向ドロップアウトアルゴリズムの研究開発

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FPGA実装のため効率的なハードウェア指向ドロップアウトアルゴリズムの研究開発

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