{"created":"2023-05-15T12:00:27.913632+00:00","id":7272,"links":{},"metadata":{"_buckets":{"deposit":"b91ba386-b400-41ad-8375-f030c7e45f90"},"_deposit":{"created_by":3,"id":"7272","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"7272"},"status":"published"},"_oai":{"id":"oai:kyutech.repo.nii.ac.jp:00007272","sets":["8:24"]},"author_link":["16176","31393","31392"],"item_21_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2019-09-23","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"113426-5","bibliographicPageStart":"113426-1","bibliographicVolumeNumber":"100-101","bibliographic_titles":[{"bibliographic_title":"Microelectronics Reliability"}]}]},"item_21_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"The non-uniform current sharing among the paralleled devices is consequential due to non-identical layout and alteration in parameters of the system consists of power semiconductor devices and gate drivers. The persistent non-uniform current among the paralleled devices arise the various concerns such as de-rating, uneven losses, and heat consequently can lead to reliability and failure issues of the system. This paper presents a simple yet intelligent and effective automatic control for gate delay compensation to achieve active current balancing through current peak minimisation. The current peak minimisation control approach can serve the purpose of minimising system de-rating as well as obtaining nearly uniform dynamic current sharing. The four parallel connected discrete IGBT system is used for experimental validation under unbalanced operating condition. Moreover, the current peak minimization trend evaluation is introduced for gate delay compensation.","subitem_description_type":"Abstract"}]},"item_21_description_60":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"subitem_description":"Journal Article","subitem_description_type":"Other"}]},"item_21_publisher_7":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"Elsevier"}]},"item_21_relation_12":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"https://doi.org/10.1016/j.microrel.2019.113426","subitem_relation_type_select":"DOI"}}]},"item_21_rights_13":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"Copyright (c) 2019 Elsevier Ltd. All rights reserved."}]},"item_21_select_59":{"attribute_name":"査読の有無","attribute_value_mlt":[{"subitem_select_item":"yes"}]},"item_21_source_id_8":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"0026-2714","subitem_source_identifier_type":"ISSN"}]},"item_21_subject_16":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"549","subitem_subject_scheme":"NDC"}]},"item_21_text_36":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Kyushu Institute of Technology, Kitakyushu, Fukuoka, Japan"},{"subitem_text_value":"Green Electronics Research Institute Kitakyushu (GRIK), Kitakyushu, Fukuoka, Japan, Kyushu Institute of Technology, Kitakyushu, Fukuoka, Japan"},{"subitem_text_value":"Kyushu Institute of Technology, Kitakyushu, Fukuoka, Japan"}]},"item_21_text_63":{"attribute_name":"連携ID","attribute_value_mlt":[{"subitem_text_value":"8019"}]},"item_21_version_type_58":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_ab4af688f83e57aa","subitem_version_type":"AM"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tripathi,  Ravi Nath"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tsukuda,  Masanori"}],"nameIdentifiers":[{}]},{"creatorAffiliations":[{"affiliationNameIdentifiers":[],"affiliationNames":[{"affiliationName":""}]}],"creatorNames":[{"creatorName":"Omura, Ichiro","creatorNameLang":"en"},{"creatorName":"大村, 一郎","creatorNameLang":"ja"},{"creatorName":"オオムラ, イチロウ","creatorNameLang":"ja-Kana"}],"familyNames":[{},{},{}],"givenNames":[{},{},{}],"nameIdentifiers":[{},{},{},{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2021-09-24"}],"displaytype":"detail","filename":"nperc136.pdf","filesize":[{"value":"775.5 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"nperc136.pdf","url":"https://kyutech.repo.nii.ac.jp/record/7272/files/nperc136.pdf"},"version_id":"f6619619-548d-4f5d-bbf6-6366b2d825fa"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Peak minimisation based gate delay compensation for active current balancing of parallel IGBT system","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Peak minimisation based gate delay compensation for active current balancing of parallel IGBT system"}]},"item_type_id":"21","owner":"3","path":["24"],"pubdate":{"attribute_name":"公開日","attribute_value":"2021-09-24"},"publish_date":"2021-09-24","publish_status":"0","recid":"7272","relation_version_is_last":true,"title":["Peak minimisation based gate delay compensation for active current balancing of parallel IGBT system"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2023-10-25T10:48:52.620605+00:00"}