@phdthesis{oai:kyutech.repo.nii.ac.jp:00007458,
 author = {Ninnart,  Fuengfusin},
 month = {2021-12-20},
 note = {1 Introduction||2 Background||3 Mixed Precision Weight Network and FPGA Design||4 Related Works||5 Experimental Results and Discussion||6 Conclusion, In this study, I introduced a mixed-precision weights network （MPWN）, which is a quantization neural network that jointly utilizes three different weight spaces: binary {-1, 1}, ternary {-1, 0, 1}, and 32-bit floating-point. I further developed the MPWN from both software and hardware aspects. From the software aspect, I evaluated the MPWN on the Fashion-MNIST, CIFAR10, and ILSVRC 2012 datasets. I systematized the accuracy sparsity bit score, which is a linear combination of accuracy, sparsity, and number of bits. This score allows Bayesian optimization to be used efficiently to search for MPWN weight space combinations. From the hardware aspect, I proposed XOR signed-bits to explore floating-point and binary weight spaces in the MPWN. XOR signed-bits is an efficient implementation equivalent to the multiplication of floating-point and binary weight spaces. Using the concept from XOR signed bits, I also provide a ternary bitwise operation that is an efficient implementation equivalent to the multiplication of floating-point and ternary weight space. To demonstrate the compatibility of the MPWN with hardware implementation, I synthesized and implemented the MPWN in a field-programmable gate array using high-level synthesis. My proposed MPWN implementation utilized up to 1.68-4.89 times less hardware resources depending on the type of resources than a conventional the 32-bit floating-point model. In addition, my implementation reduced the latency up to 31.55 times compared to 32-bit floating-point model without optimizations., 九州工業大学博士学位論文 学位記番号：生工博甲第419号 学位授与年月日：令和3年9月24日, 令和3年度},
 school = {九州工業大学},
 title = {Mixed-precision weights network for field-programmable gate array},
 year = {}
}