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Effect of cell size reduction on the threshold voltage of UMOSFETs
http://hdl.handle.net/10228/00008943
http://hdl.handle.net/10228/00008943faf62000-1da4-4ac7-95c7-e08e60aae6bc
| 名前 / ファイル | ライセンス | アクション |
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nperc154.pdf (668.5 kB)
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| Item type | 学術雑誌論文 = Journal Article(1) | |||||||||||||
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| 公開日 | 2022-07-14 | |||||||||||||
| 資源タイプ | ||||||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||||||
| 資源タイプ | journal article | |||||||||||||
| タイトル | ||||||||||||||
| タイトル | Effect of cell size reduction on the threshold voltage of UMOSFETs | |||||||||||||
| 言語 | en | |||||||||||||
| 言語 | ||||||||||||||
| 言語 | eng | |||||||||||||
| 著者 |
Baba, Yoshiro
× Baba, Yoshiro× 大村, 一郎
WEKO
16176
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| 抄録 | ||||||||||||||
| 内容記述タイプ | Abstract | |||||||||||||
| 内容記述 | UMOSFET on-resistances have been dramatically improved in recent decades with the miniaturization of cell size by innovations in the fabrication process. However, with miniaturization, failure in the gate oxide, large deviations in the threshold voltage and reductions in avalanche capability have emerged as design problems for mass production. In particular, threshold voltage increase have appeared with the introduction of a trench source contact. The source contact trench and MOS gate trench are fabricated next to each other with a narrow silicon mesa region, and the voltage increase appear when the silicon mesa width becomes narrower than 80 nm. So far, it appears that the P+ layer dopant in the contact sidewall diffuses toward the gate oxide and the channel doping increases, which causes the increase in the threshold voltage Vth. We analyzed the distribution of Vth at the wafer level/shot level and found for the first time that the increase in Vth is caused by the punch-through effect from the channel depletion layer to the contact P+ layer, and thus, sidewall dopant diffusion will not affect the increase in Vth. We established an analytical model for the increase in Vth. Our model showed that for the field plate type UMOSFET with a shorter gate contact length, not only is there a increase in Vth, but also it is difficult to control Vth using the conventional channel implantation method. | |||||||||||||
| 言語 | en | |||||||||||||
| 書誌情報 |
en : Microelectronics Reliability 巻 114, p. 113747-1-113747-6, 発行日 2020-07-14 |
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| 出版社 | ||||||||||||||
| 出版者 | Elsevier | |||||||||||||
| DOI | ||||||||||||||
| 関連タイプ | isVersionOf | |||||||||||||
| 識別子タイプ | DOI | |||||||||||||
| 関連識別子 | https://doi.org/10.1016/j.microrel.2020.113747 | |||||||||||||
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| 収録物識別子タイプ | PISSN | |||||||||||||
| 収録物識別子 | 0026-2714 | |||||||||||||
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| 収録物識別子タイプ | EISSN | |||||||||||||
| 収録物識別子 | 1872-941X | |||||||||||||
| 著作権関連情報 | ||||||||||||||
| 権利情報 | Copyright (c) 2020 Elsevier Ltd. All rights reserved. | |||||||||||||
| 出版タイプ | ||||||||||||||
| 出版タイプ | AM | |||||||||||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||||||||||
| 査読の有無 | ||||||||||||||
| 値 | yes | |||||||||||||
| 連携ID | ||||||||||||||
| 値 | 8512 | |||||||||||||
