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DART: Dependable VLSI Test Architecture and Its Implementation
http://hdl.handle.net/10228/00006255
http://hdl.handle.net/10228/00006255bf568409-5d50-46f7-b5fa-43c795e5a31b
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
itc_2012.pdf (669.9 kB)
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| アイテムタイプ | 会議発表論文 = Conference Paper(1) | |||||
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| 公開日 | 2017-07-11 | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||
| 資源タイプ | conference paper | |||||
| タイトル | ||||||
| タイトル | DART: Dependable VLSI Test Architecture and Its Implementation | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 著者 |
Sato, Yasuo
× Sato, Yasuo× 梶原, 誠司× Yoneda, Tomokazu× Hatayama, Kazumi× Inoue, Michiko× Miura, Yukiya× Ohtake, Satoshi× Hasegawa, Takumi× Sato, Motoyuki× Shimamura, Kotaro |
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| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | Although many electronic safety-related systems require very high reliability, it is becoming harder and harder to achieve it because of delay-related failures, which are caused by decreased noise margin. This paper describes a technology named DART and its implementation. The DART repeatedly measures the maximum delay of a circuit and the amount of degradation in field, in consequence, confirms the marginality of the circuit. The system employing the DART will be informed the significant reduction of delay margin in advance of a failure and be able to repair it at an appropriate time. The DART also equips a technique to improve the test coverage using the rotating test and a technique to consider the test environment such as temperature or voltage using novel ring-oscillator-based monitors. The authors applied the proposed technology to an industrial design and confirmed its effectiveness and availability with reasonable resources. | |||||
| 言語 | en | |||||
| 備考 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 2012 IEEE International Test Conference, 5-8 November 2012, Anaheim, CA, USA | |||||
| 書誌情報 |
en : 2012 IEEE International Test Conference 発行日 2013-01-07 |
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| 出版社 | ||||||
| 出版社 | IEEE | |||||
| DOI | ||||||
| 関連タイプ | isVersionOf | |||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | https://doi.org/10.1109/TEST.2012.6401581 | |||||
| ISBN | ||||||
| 識別子タイプ | ISBN | |||||
| 関連識別子 | 978-1-4673-1595-1 | |||||
| ISBN | ||||||
| 識別子タイプ | ISBN | |||||
| 関連識別子 | 978-1-4673-1594-4 | |||||
| ISBN | ||||||
| 識別子タイプ | ISBN | |||||
| 関連識別子 | 978-1-4673-1593-7 | |||||
| ISSN | ||||||
| 収録物識別子タイプ | EISSN | |||||
| 収録物識別子 | 2378-2250 | |||||
| ISSN | ||||||
| 収録物識別子タイプ | PISSN | |||||
| 収録物識別子 | 1089-3539 | |||||
| 著作権関連情報 | ||||||
| 権利情報 | Copyright (c) 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||
| 出版タイプ | ||||||
| 出版タイプ | AM | |||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
| 査読の有無 | ||||||
| 値 | yes | |||||
| 研究者情報 | ||||||
| URL | https://hyokadb02.jimu.kyutech.ac.jp/html/201_ja.html | |||||
| 論文ID（連携） | ||||||
| 値 | 10282569 | |||||
| 連携ID | ||||||
| 値 | 6194 | |||||
