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アイテム
Time and Space Redundancy Fault Tolerance Trade-offs for FPGA Based Single and Multicore Designs
http://hdl.handle.net/10228/00007243
http://hdl.handle.net/10228/00007243cf622c38-0c0d-4f5e-90e6-abba4ccf30f8
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
LaSEINE-2014_07.pdf (1.1 MB)
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| アイテムタイプ | 会議発表論文 = Conference Paper(1) | |||||||||
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| 公開日 | 2019-06-25 | |||||||||
| 資源タイプ | ||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||||||
| 資源タイプ | conference paper | |||||||||
| タイトル | ||||||||||
| タイトル | Time and Space Redundancy Fault Tolerance Trade-offs for FPGA Based Single and Multicore Designs | |||||||||
| 言語 | en | |||||||||
| 言語 | ||||||||||
| 言語 | eng | |||||||||
| 著者 |
Ibrahim, Mohamed Mahmoud
× Ibrahim, Mohamed Mahmoud× 浅海, 賢一
WEKO
24725
× 趙, 孟佑 |
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| 抄録 | ||||||||||
| 内容記述タイプ | Abstract | |||||||||
| 内容記述 | This paper investigates the gains and losses in terms of power, area, reliability, and speed when applying time redundancy fault tolerance techniques on single core designs compared to space redundancy fault tolerance techniques applied to multi-core designs. The system is developed on the virtex5 FPGA from Xilinx, it uses 65nm technology with a relatively moderate to high static power consumption. The system consists of two design alternatives. The first is a single core embedded processing system that applies time redundancy fault tolerance through execution repetition to perform self-check pointing through consensus. The second system is built from 3 soft IP core processors which perform a space redundancy approach through Triple-Modular-Redundancy (TMR) with feedback among the processors. The performance of both systems is evaluated in terms of the execution speed and latency due to fault tolerance techniques compared to the non-fault tolerant system. | |||||||||
| 備考 | ||||||||||
| 内容記述タイプ | Other | |||||||||
| 内容記述 | 29th International Symposium on Space Technology and Science (ISTS), June 2 to June 9, 2013, Nagoya City, Aichi | |||||||||
| 書誌情報 |
Transactions of the Japan Society for Aeronautical and Space Sciences, Aerospace Technology Japan 巻 12, 号 ists29, p. Pj_15-Pj_24, 発行日 2013-06-07 |
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| 出版社 | ||||||||||
| 出版社 | 日本航空宇宙学会 | |||||||||
| DOI | ||||||||||
| 関連タイプ | isIdenticalTo | |||||||||
| 識別子タイプ | DOI | |||||||||
| 関連識別子 | https://doi.org/10.2322/tastj.12.Pj_15 | |||||||||
| NAID | ||||||||||
| 関連タイプ | isIdenticalTo | |||||||||
| 識別子タイプ | NAID | |||||||||
| 関連識別子 | 130004706673 | |||||||||
| ISSN | ||||||||||
| 収録物識別子タイプ | PISSN | |||||||||
| 収録物識別子 | 1884-0485 | |||||||||
| 著作権関連情報 | ||||||||||
| 権利情報 | Copyright (c) 2014 by the Japan Society for Aeronautical and Space Sciences and ISTS. | |||||||||
| キーワード | ||||||||||
| 主題Scheme | Other | |||||||||
| 主題 | Multicore Systems | |||||||||
| キーワード | ||||||||||
| 主題Scheme | Other | |||||||||
| 主題 | Fault Tolerance | |||||||||
| キーワード | ||||||||||
| 主題Scheme | Other | |||||||||
| 主題 | Space Redundancy | |||||||||
| キーワード | ||||||||||
| 主題Scheme | Other | |||||||||
| 主題 | Time Redundancy | |||||||||
| キーワード | ||||||||||
| 主題Scheme | Other | |||||||||
| 主題 | FPGA | |||||||||
| 出版タイプ | ||||||||||
| 出版タイプ | VoR | |||||||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||||
| 査読の有無 | ||||||||||
| 値 | yes | |||||||||
| 連携ID | ||||||||||
| 値 | 7690 | |||||||||
