WEKO3
アイテム
On-Chip Test Clock Validation Using A Time-to-Digital Converter in FPGAs
http://hdl.handle.net/10228/00007522
http://hdl.handle.net/10228/00007522462e1da5-bec0-465f-ada5-11bf6dd4800c
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
10348703.pdf (1.4 MB)
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| アイテムタイプ | 会議発表論文 = Conference Paper(1) | |||||||||||
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| 公開日 | 2020-01-10 | |||||||||||
| 資源タイプ | ||||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||||||||
| 資源タイプ | conference paper | |||||||||||
| タイトル | ||||||||||||
| タイトル | On-Chip Test Clock Validation Using A Time-to-Digital Converter in FPGAs | |||||||||||
| 言語 | en | |||||||||||
| その他のタイトル | ||||||||||||
| その他のタイトル | On-chip test clock validation using a time-to-digital converter in FPGAs | |||||||||||
| 言語 | en | |||||||||||
| 言語 | ||||||||||||
| 言語 | eng | |||||||||||
| 著者 |
Miyake, Yousuke
× Miyake, Yousuke× 梶原, 誠司
WEKO
1147
× Chen, Poki |
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| 抄録 | ||||||||||||
| 内容記述タイプ | Abstract | |||||||||||
| 内容記述 | While on-chip delay measurement combining logic BIST with a variable test clock is an effective way to secure field reliability of VLSI/FPGAs, validation of the variable test clock generated on the chip is important to guarantee measurement accuracy. This paper addresses a method of on-chip test clock validation using a TDC (Time-to-Digital Converter) for FPGAs. The proposed method has two operation modes, one is a resolution measurement mode and the other is a phase difference measurement mode. The resolution measurement mode is performed first to check the resolution of the TDC circuit. The phase difference measurement mode checks the timing difference between the original clock and the generated test clock. Evaluation experiments using a real FPGA device shows that the resolution of the proposed clock validation method using a TDC is 50.46 ps. For a variable test clock with resolution of 96.15 ps, it was confirmed that INL (Integral Non-Linearity) of the clock is within 10% and it was inconsistent with a result observed by an oscilloscope. | |||||||||||
| 備考 | ||||||||||||
| 内容記述タイプ | Other | |||||||||||
| 内容記述 | The 3rd International Test Conference in Asia (ITC-Asia 2019), September 3-5, 2019Tokyo Denki University, Tokyo, Japan | |||||||||||
| 書誌情報 |
2019 IEEE International Test Conference in Asia (ITC-Asia) 発行日 2019-10-17 |
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| 出版社 | ||||||||||||
| 出版社 | IEEE | |||||||||||
| DOI | ||||||||||||
| 関連タイプ | isVersionOf | |||||||||||
| 識別子タイプ | DOI | |||||||||||
| 関連識別子 | https://doi.org/10.1109/ITC-Asia.2019.00040 | |||||||||||
| ISBN | ||||||||||||
| 識別子タイプ | ISBN | |||||||||||
| 関連識別子 | 978-1-7281-4718-5 | |||||||||||
| ISBN | ||||||||||||
| 識別子タイプ | ISBN | |||||||||||
| 関連識別子 | 978-1-7281-4719-2 | |||||||||||
| 著作権関連情報 | ||||||||||||
| 権利情報 | Copyright (c) 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||||||||
| キーワード | ||||||||||||
| 主題Scheme | Other | |||||||||||
| 主題 | FPGA | |||||||||||
| キーワード | ||||||||||||
| 主題Scheme | Other | |||||||||||
| 主題 | Built-In Self-Test | |||||||||||
| キーワード | ||||||||||||
| 主題Scheme | Other | |||||||||||
| 主題 | Delay testing | |||||||||||
| キーワード | ||||||||||||
| 主題Scheme | Other | |||||||||||
| 主題 | Variable test clock | |||||||||||
| キーワード | ||||||||||||
| 主題Scheme | Other | |||||||||||
| 主題 | Time-to-Digital Converter | |||||||||||
| 出版タイプ | ||||||||||||
| 出版タイプ | AM | |||||||||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||||||||
| 査読の有無 | ||||||||||||
| 値 | yes | |||||||||||
| 研究者情報 | ||||||||||||
| URL | https://hyokadb02.jimu.kyutech.ac.jp/html/201_ja.html | |||||||||||
| 論文ID（連携） | ||||||||||||
| 値 | 10348703 | |||||||||||
| 連携ID | ||||||||||||
| 値 | 8031 | |||||||||||
