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A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips
http://hdl.handle.net/10228/00008139
http://hdl.handle.net/10228/000081393e80f436-2e5b-4a56-ac59-e30e301f1a46
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
10362951.pdf (1.6 MB)
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| アイテムタイプ | 学術雑誌論文 = Journal Article(1) | |||||
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| 公開日 | 2021-04-06 | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | journal article | |||||
| タイトル | ||||||
| タイトル | A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 著者 |
Kato, Takaaki
× Kato, Takaaki× Wang, Senling× Sato, Yasuo× 梶原, 誠司× 温, 暁青 |
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| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | High power dissipation in scan-based logic built-in self-test (LBIST) is a crucial issue that can cause over-testing, reliability degradation, chip damage, and so on. While many sophisticated approaches to low-power testing have been proposed in the past, it remains a serious problem to control the test power of LBIST to a predetermined appropriate level that matches the power requirements of the circuit-under-test. This paper proposes a novel power-control method for LBIST that can control the scan-shift power to an arbitrary level. The proposed method modifies pseudo-random patterns generated by an embedded test pattern generator (TPG) so that the modified patterns have the specific toggle rate without sacrificing fault coverage and test time. In order to evaluate the effectiveness of the proposed method, this paper shows not only simulation-based experimental results but also measurement results on test element group (TEG) chips. | |||||
| 言語 | en | |||||
| 書誌情報 |
IEEE Transactions on Emerging Topics in Computing 巻 8, 号 3, p. 591-601, 発行日 2020-09-01 |
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| 出版社 | ||||||
| 出版者 | IEEE | |||||
| DOI | ||||||
| 関連タイプ | isVersionOf | |||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | https://doi.org/10.1109/TETC.2017.2767070 | |||||
| 日本十進分類法 | ||||||
| 主題Scheme | NDC | |||||
| 主題 | 549 | |||||
| ISSN | ||||||
| 収録物識別子タイプ | EISSN | |||||
| 収録物識別子 | 2168-6750 | |||||
| ISSN | ||||||
| 収録物識別子タイプ | PISSN | |||||
| 収録物識別子 | 2376-4562 | |||||
| 著作権関連情報 | ||||||
| 権利情報 | Copyright (c) 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Logic BIST | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | low power test | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | scan design | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | scan-in power control | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | pseudo-random pattern | |||||
| 出版タイプ | ||||||
| 出版タイプ | AM | |||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
| 査読の有無 | ||||||
| 値 | yes | |||||
| 研究者情報 | ||||||
| URL | https://hyokadb02.jimu.kyutech.ac.jp/html/201_ja.html | |||||
| 論文ID（連携） | ||||||
| 値 | 10362951 | |||||
| 連携ID | ||||||
| 値 | 8663 | |||||
