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Mixed-precision weights network for field-programmable gate array
http://hdl.handle.net/10228/00008263
http://hdl.handle.net/10228/0000826353baad9b-5c26-4b5e-abc2-d33dfe6d9c5a
| 名前 / ファイル | ライセンス | アクション |
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journal.pone.0251329.pdf (1.5 MB)
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| Item type | 学術雑誌論文 = Journal Article(1) | |||||||||||||
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| 公開日 | 2021-05-20 | |||||||||||||
| 資源タイプ | ||||||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||||||
| 資源タイプ | journal article | |||||||||||||
| タイトル | ||||||||||||||
| タイトル | Mixed-precision weights network for field-programmable gate array | |||||||||||||
| 言語 | en | |||||||||||||
| 言語 | ||||||||||||||
| 言語 | eng | |||||||||||||
| 著者 |
Fuengfusin, Ninnart
× Fuengfusin, Ninnart× 田向, 権
WEKO
6059
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| 抄録 | ||||||||||||||
| 内容記述タイプ | Abstract | |||||||||||||
| 内容記述 | In this study, we introduced a mixed-precision weights network (MPWN), which is a quantization neural network that jointly utilizes three different weight spaces: binary {−1,1}, ternary {−1,0,1}, and 32-bit floating-point. We further developed the MPWN from both software and hardware aspects. From the software aspect, we evaluated the MPWN on the Fashion-MNIST and CIFAR10 datasets. We systematized the accuracy sparsity bit score, which is a linear combination of accuracy, sparsity, and number of bits. This score allows Bayesian optimization to be used efficiently to search for MPWN weight space combinations. From the hardware aspect, we proposed XOR signed-bits to explore floating-point and binary weight spaces in the MPWN. XOR signed-bits is an efficient implementation equivalent to multiplication of floating-point and binary weight spaces. Using the concept from XOR signed bits, we also provide a ternary bitwise operation that is an efficient implementation equivalent to the multiplication of floating-point and ternary weight space. To demonstrate the compatibility of the MPWN with hardware implementation, we synthesized and implemented the MPWN in a field-programmable gate array using high-level synthesis. Our proposed MPWN implementation utilized up to 1.68-4.89 times less hardware resources depending on the type of resources than a conventional 32-bit floating-point model. In addition, our implementation reduced the latency up to 31.55 times compared to 32-bit floating-point model without optimizations. | |||||||||||||
| 言語 | en | |||||||||||||
| 書誌情報 |
en : PLoS ONE 巻 16, 号 5, p. e0251329, 発行日 2021-05-10 |
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| 出版社 | ||||||||||||||
| 出版者 | Public Library of Science | |||||||||||||
| 言語 | en | |||||||||||||
| DOI | ||||||||||||||
| 関連タイプ | isIdenticalTo | |||||||||||||
| 識別子タイプ | DOI | |||||||||||||
| 関連識別子 | https://doi.org/10.1371/journal.pone.0251329 | |||||||||||||
| 日本十進分類法 | ||||||||||||||
| 主題Scheme | NDC | |||||||||||||
| 主題 | 548 | |||||||||||||
| ISSN | ||||||||||||||
| 収録物識別子タイプ | EISSN | |||||||||||||
| 収録物識別子 | 1932-6203 | |||||||||||||
| 著作権関連情報 | ||||||||||||||
| 権利情報 | Copyright (c) 2021 Fuengfusin, Tamukoh. | |||||||||||||
| 著作権関連情報 | ||||||||||||||
| 権利情報Resource | http://creativecommons.org/licenses/by/4.0/ | |||||||||||||
| 権利情報 | This is an open access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited. | |||||||||||||
| 出版タイプ | ||||||||||||||
| 出版タイプ | VoR | |||||||||||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||||||||
| 査読の有無 | ||||||||||||||
| 値 | yes | |||||||||||||
| 研究者情報 | ||||||||||||||
| URL | https://hyokadb02.jimu.kyutech.ac.jp/html/100000641_ja.html | |||||||||||||
| 論文ID（連携） | ||||||||||||||
| 値 | 10364473 | |||||||||||||
| 連携ID | ||||||||||||||
| 値 | 8846 | |||||||||||||
