WEKO3
アイテム
耐ソフトエラーラッチにおける欠陥の分析、検出及び評価に関する研究
https://doi.org/10.18997/00009010
https://doi.org/10.18997/000090101c62fd3a-8404-493e-bf95-514b5643b668
| 名前 / ファイル | ライセンス | アクション |
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jou_k_371.pdf (1.5 MB)
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| アイテムタイプ | 学位論文 = Thesis or Dissertation(1) | |||||||
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| 公開日 | 2022-11-28 | |||||||
| 資源タイプ | ||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_db06 | |||||||
| 資源タイプ | doctoral thesis | |||||||
| タイトル | ||||||||
| タイトル | Defects in Hardened Latches: Analysis, Detection and Evaluation | |||||||
| 言語 | en | |||||||
| タイトル | ||||||||
| タイトル | 耐ソフトエラーラッチにおける欠陥の分析、検出及び評価に関する研究 | |||||||
| 言語 | ja | |||||||
| 言語 | ||||||||
| 言語 | eng | |||||||
| 著者 |
Ma, Ruijun
× Ma, Ruijun
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| 抄録 | ||||||||
| 内容記述タイプ | Abstract | |||||||
| 内容記述 | The development of modern integrated circuits （ICs） has greatly changed the life of humankind. Nowadays, IC s are also indispensable to mission-critical applications, such as medical devices, autonomous cars, aircraft navigating systems, and satellites. The reliability of these mission-critical applications is a major concern. A soft-error occurring in an IC is a severe threat to its reliability, especially for mission-critical applications. The continuous trend of shrinking technology feature sizes makes modern ICs more and more vulnerable to soft errors. Soft-errors are caused by radiation particles striking an IC and generating current pulses to disturb its functionality. A soft-error can cause data corruption and may eventually lead to system failure s If a soft-error occurs in an operational medical device during surgery, it may cause a malfunction of this device and interrupt the surgery process. A soft-error may change the control data of an autonomous car which may lead to an accident. A soft-error may corrupt the aircraft navigating systems. No one would take the chance to let it happen even though malfunction s caused by soft errors can be solved by resetting these devices. Because reset takes time and severe results may happen during the resetting. If a soft-error causes a malfunction in the control system of a satellite, it may not be able to maintain its height and eventually burn up as it falls into the Earth’s atmosphere. Hence, it is important to protect ICs from soft errors. Many soft-error tolerance methods have been proposed to protect ICs against soft-errors. In an IC, memory elements and storage elements （e.g., latches and flip flops） are the most vulnerable to soft-errors, and data stored in them are crucial to the operation of a circuit. Error correction codes （ECCs） can be u sed to protect memories. Register-level soft-error tolerance methods can be used to detect soft-errors in latches by using parity checking and correct them by resetting. Hardened designs protect latches against soft-errors by using redundant feedback loops to store the same input data and using a voter to select the correct output. The advantage of using hardened designs is that they can prevent soft-errors from reaching outputs while ECCs and register-level soft-error tolerance methods must detect soft-errors and then correct them by restoring the data. For protecting storage elements in mission-critical applications, hardened latch design is the best option because it has high reliability and can save the resetting time. Many state-of-the-art hardened latch designs have been proposed to tolerate soft errors and they are believed to have good soft-error tolerability. Defects （physical flaws due to imperfect production （production defects） and physical changes caused by aging effects after a long operation time （aging-related defects） can also cause a malfunction of a circuit and cause a system failure eventually. Different from the temporal state change of a circuit caused by soft errors, defects are permanent damages to a circuit and can disturb the behavior of a circuit from its desired manner. Defects in storage elements should be detected to make sure a system/device operating correctly and stably. Scan test is a commonly used defect detection method, which connects reconfigured storage elements to form a shift register with external access and the internal states of these storage elements can be easily controlled and checked. However, the impact of defects on existing state of the art hardened latch design has not been considered. This impact requires consideration because added redundancy in hardened latch designs can not only mask soft-errors but also mask the effects of defects and it can lead to two serious problems: Problem-1 （Low Testability）: Production defects in hardened latch designs are difficult to detect with conventional scan tests, in which the observability （an important metric to evaluate a circuit’s testability） of defects in hardened latch designs can be greatly reduced. Therefore, existing state-of-the-art hardened latches have low observability and thus low testability. Furthermore, defects that escaped the production test （undetected defects） may become more and more serious and cause a system failure eventually. Problem-2 （Low Soft-Error Tolerability）: Undetected defects and aging-related defects can make hardened latch designs vulnerable to soft-errors while defect-free ones do not. The soft-error tolerability of hardened latch designs may be compromise d by undetected defects or aging related defects. This research is the first to consider Problem-1 of low testability of hardened latches and Problem-2 of defects reducing the reliability of hardened latches. Furthermore, this research is the first to pro pose a comprehensive solution to solve these two problems with the following five major contributions: Contribution-1: A first of its kind metric for quantifying the impact of defects on hardened latches, called Post-Test Vulnerability Factor （PTVF）. It is used to analyze the residual soft-error tolerability of hardened latches after testing. Problem-2 is solved by this first major contribution. Contribution-2: A novel design called Scan-Test-Aware Hardened Latch （STAHL） that provides the highest defect coverage in comparison with all existing hardened latches. Problem-1 is solved by using STAHL to build a scan c ell to perform a scan test. Contribution-3: A novel scan test procedure is proposed to solve Problem-1 by fully testing the STAHL based scan cell. Contribution-4: A novel High-Performance Scan-Test-Aware Hardened Latch （HP-STAHL） design can also solve Problem-1 and has similar defect coverage as STAHL but has lower power consumption and higher propagation speed. Contribution-5: A novel scan test procedure is proposed to fully test the HP STAHL-based scan cell to solve Problem-1. Comprehensive simulation results demonstrate the accuracy of the PTVF metric and the effectiveness of the STAHL-based scan test and HP-STAHL-based scan test. As the first comprehensive study bridging the gap between hardened latch design s and IC testing, the findings of this research are expected to significantly improve the soft-error-related reliability of IC designs for mission-critical applications. Furthermore, the two proposed hardened latches and the scan test procedures can not only be use d to detect defects after production but also can be applied to detect aging related defects in the field through performing built-in self-test （BIST）. In Chapter 1, an example is introduced to indicate Problem-1 and Problem-2. Chapter 2 shows the background information of soft-errors and defects. Chapter 3 shows some typical soft-error mitigation methods and details of a scan test. Chapter 4 describes the detailed information of PTVF Contribution-1）. Chapter 5 shows the structure of STAHL （Contribution-2） and Chapter 6 shows the scan test procedure of testing the STAHL-based scan cell （Contribution-3）. Chapter 7 shows the structure of HP-STAHL （Contribution-4） and Chapter 8 shows the scan test procedure of testing the HP-STAHL based scan cell （Contribution-5）. Chapter 9 shows the experimental results of comparing STAHL and HP-STAHL with state-of-the-art hardened latch designs. Chapter 10 concludes this thesis. | |||||||
| 言語 | en | |||||||
| 目次 | ||||||||
| 内容記述タイプ | TableOfContents | |||||||
| 内容記述 | 1. Introduction||2. Background||3. Related Works||4. Post-Test Vulnerability Factor （PTVF）||5. Scan-Test Aware Hardened Latch （STAHL）||6. Scan Test Based on STAHL||7. High Performance Scan-Test-Aware Hardened Latch （HP STAHL）||8. Scan Test Based on HP STAHL||9. Experimental Evaluation||10. Conclusions and Future Works | |||||||
| 備考 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | 九州工業大学博士学位論文 学位記番号：情工博甲第371号 学位授与年月日：令和4年9月26日 | |||||||
| キーワード | ||||||||
| 主題Scheme | Other | |||||||
| 主題 | soft error | |||||||
| キーワード | ||||||||
| 主題Scheme | Other | |||||||
| 主題 | hardened latch | |||||||
| キーワード | ||||||||
| 主題Scheme | Other | |||||||
| 主題 | defect | |||||||
| キーワード | ||||||||
| 主題Scheme | Other | |||||||
| 主題 | scan test | |||||||
| アドバイザー | ||||||||
| 温, 暁青 | ||||||||
| 学位授与番号 | ||||||||
| 学位授与番号 | 甲第371号 | |||||||
| 学位名 | ||||||||
| 学位名 | 博士（情報工学） | |||||||
| 学位授与年月日 | ||||||||
| 学位授与年月日 | 2022-09-26 | |||||||
| 学位授与機関 | ||||||||
| 学位授与機関識別子Scheme | kakenhi | |||||||
| 学位授与機関識別子 | 17104 | |||||||
| 学位授与機関名 | 九州工業大学 | |||||||
| 学位授与年度 | ||||||||
| 内容記述タイプ | Other | |||||||
| 内容記述 | 令和4年度 | |||||||
| 出版タイプ | ||||||||
| 出版タイプ | VoR | |||||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||
| アクセス権 | ||||||||
| アクセス権 | open access | |||||||
| アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||||
| ID登録 | ||||||||
| ID登録 | 10.18997/00009010 | |||||||
| ID登録タイプ | JaLC | |||||||
